{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,24]],"date-time":"2026-07-24T18:49:25Z","timestamp":1784918965340,"version":"3.55.0"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency (DARPA)\u2019s Automatic Implementation of Secure Silicon Program","doi-asserted-by":"publisher","award":["M2002062"],"award-info":[{"award-number":["M2002062"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Global Ph.D. Fellowship at NYU\/NYU AD"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2021,9]]},"DOI":"10.1109\/tcad.2020.3029133","type":"journal-article","created":{"date-parts":[[2020,10,6]],"date-time":"2020-10-06T19:35:32Z","timestamp":1602012932000},"page":"1740-1753","source":"Crossref","is-referenced-by-count":77,"title":["Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking"],"prefix":"10.1109","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1504-2575","authenticated-orcid":false,"given":"Nimisha","family":"Limaye","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4687-4152","authenticated-orcid":false,"given":"Emmanouil","family":"Kalligeros","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nikolaos","family":"Karousos","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5187-3766","authenticated-orcid":false,"given":"Irene G.","family":"Karybali","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0782-0397","authenticated-orcid":false,"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2018.8624866"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516654"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714955"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060458"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.24"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_28"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/VTS48691.2020.9107641"},{"key":"ref35","volume":"17","author":"bushnell","year":"2004","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0687"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2915606"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2356453"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2019.2940750"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942047"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116197"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.284"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2801220"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2968898"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2019.2904838"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228377"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-15334-2_2"},{"key":"ref6","year":"2012","journal-title":"iPhone 5 A6 SoC reverse engineered reveals rare hand-made custom CPU and tri-core GPU"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715163"},{"key":"ref5","year":"2012","journal-title":"Intel’s 22-nm Trigate Transistors Exposed"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797019"},{"key":"ref7","author":"karmakar","year":"2018","journal-title":"Encrypt flip-flop A novel logic encryption technique for sequential circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2019.12.007"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772817"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116463"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060469"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951805"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-66787-4_10"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715053"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203757"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9518291\/9214869-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9518291\/09214869.pdf?arnumber=9214869","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:49:31Z","timestamp":1652194171000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9214869\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9]]},"references-count":40,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.3029133","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,9]]}}}