{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,15]],"date-time":"2026-07-15T10:12:21Z","timestamp":1784110341436,"version":"3.55.0"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100001711","name":"Swiss National Science Foundation","doi-asserted-by":"publisher","award":["200021-169084 MAJesty"],"award-info":[{"award-number":["200021-169084 MAJesty"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]},{"name":"EPFL Open Science Fund"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2867.001"],"award-info":[{"award-number":["2867.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/tcad.2020.3032625","type":"journal-article","created":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T13:35:55Z","timestamp":1603287355000},"page":"2184-2188","source":"Crossref","is-referenced-by-count":17,"title":["Three-Input Gates for Logic Synthesis"],"prefix":"10.1109","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4438-307X","authenticated-orcid":false,"given":"Dewmini Sudara","family":"Marakkalage","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1114-8476","authenticated-orcid":false,"given":"Eleonora","family":"Testa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1527-7160","authenticated-orcid":false,"given":"Heinz","family":"Riener","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0229-8766","authenticated-orcid":false,"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7827-3215","authenticated-orcid":false,"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"747","article-title":"Some theorems useful in threshold logic for enumerating Boolean functions","author":"goto","year":"1962","journal-title":"Proc IFIP Congr"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/0165-1684(85)90052-0"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02777-2_5"},{"key":"ref13","author":"knuth","year":"2015","journal-title":"The Art of Computer Programming Volume 4 Fascicle 6 Satisfiability"},{"key":"ref14","article-title":"The EPFL combinational benchmark suite","author":"amar\u00fa","year":"2015","journal-title":"Proc 24th Int Workshop Logic Synth (IWLS)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342027"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2897703"},{"key":"ref17","article-title":"Practical SAT&#x2014;A tutorial on applied satisfiability solving","author":"e\u00e9n","year":"2007","journal-title":"Proc FMCAD"},{"key":"ref18","author":"soeken","year":"2019","journal-title":"The EPFL logic synthesis libraries"},{"key":"ref19","first-page":"502","article-title":"An extensible SAT-solver","author":"e\u00e9n","year":"2003","journal-title":"Proc Int Conf Theory Appl Satisfiability Test"},{"key":"ref4","author":"muroga","year":"1979","journal-title":"Logic Design and Switching Theory"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317905"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270347"},{"key":"ref5","first-page":"204","article-title":"The yorktown silicon compiler","author":"brayton","year":"1988","journal-title":"Silicon Compilation"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382541"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2869760"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9540731\/09233431.pdf?arnumber=9233431","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:43:41Z","timestamp":1641987821000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9233431\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":19,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.3032625","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,10]]}}}