{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,16]],"date-time":"2026-04-16T00:00:20Z","timestamp":1776297620391,"version":"3.50.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"German Research Foundation (DFG) funded Project ReAp","doi-asserted-by":"publisher","award":["380524764"],"award-info":[{"award-number":["380524764"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,2]]},"DOI":"10.1109\/tcad.2021.3056337","type":"journal-article","created":{"date-parts":[[2021,2,3]],"date-time":"2021-02-03T06:13:40Z","timestamp":1612332820000},"page":"211-224","source":"Crossref","is-referenced-by-count":114,"title":["High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9774-9522","authenticated-orcid":false,"given":"Salim","family":"Ullah","sequence":"first","affiliation":[{"name":"Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany"}]},{"given":"Semeen","family":"Rehman","sequence":"additional","affiliation":[{"name":"Institute of Computer Technology, Technische Universit&#x00E4;t Wien, Vienna, Austria"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2607-8135","authenticated-orcid":false,"given":"Muhammad","family":"Shafique","sequence":"additional","affiliation":[{"name":"Division of Engineering, New York University Abu Dhabi, Abu Dhabi, UAE"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7125-1737","authenticated-orcid":false,"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[{"name":"Chair for Processor Design, Technische Universit&#x00E4;t Dresden, Dresden, Germany"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"7 Series DSP48E1 Slice","year":"2018"},{"key":"ref2","volume-title":"LogiCORE IP V12.0","year":"2015"},{"key":"ref3","volume-title":"Integer Arithmetic IP Cores User Guide","year":"2020"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645544"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.102"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.12.012"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2017.35"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3390\/computers5040020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2015.17"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.48"},{"key":"ref11","volume-title":"7 Series FPGAs Configurable Logic Block","year":"2016"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272301"},{"key":"ref13","volume-title":"Computer Arithmetic Algorithms and Hardware Designs","author":"Parhami","year":"2000"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"issue":"5","key":"ref15","article-title":"Some schemes for parallel multipliers","volume":"34","author":"Dadda","year":"1965","journal-title":"Alta frequenza"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1992.271307"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484850"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744778"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228509"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783335"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372600"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.108"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657022"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/GET.2015.7453816"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993675"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926993"},{"key":"ref31","volume-title":"Vivado Design Suite User Guide","year":"2017"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465845"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465781"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2988404"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.2995053"},{"key":"ref36","volume-title":"SIPI Image Database","year":"2019"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223648"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2906199"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645543"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1093\/qjmam\/4.2.236"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-70928-2_64"},{"key":"ref44","volume-title":"MNIST-cnn","year":"2016"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9686308\/09344673.pdf?arnumber=9344673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,9]],"date-time":"2024-01-09T23:44:43Z","timestamp":1704843883000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9344673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2]]},"references-count":44,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3056337","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,2]]}}}