{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:00:38Z","timestamp":1740132038665,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2022,3,1]],"date-time":"2022-03-01T00:00:00Z","timestamp":1646092800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,3,1]],"date-time":"2022-03-01T00:00:00Z","timestamp":1646092800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,3,1]],"date-time":"2022-03-01T00:00:00Z","timestamp":1646092800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,3]]},"DOI":"10.1109\/tcad.2021.3068097","type":"journal-article","created":{"date-parts":[[2021,3,23]],"date-time":"2021-03-23T20:27:29Z","timestamp":1616531249000},"page":"571-582","source":"Crossref","is-referenced-by-count":1,"title":["Causal Path Identification for Timed and Sequential Circuits"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5426-9561","authenticated-orcid":false,"given":"Mackenzie J.","family":"Wibbels","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenneth S.","family":"Stevens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TSMC.1973.4309232"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1961.28"},{"key":"ref3","volume-title":"The Art of Computer Programming","volume":"1","author":"Kunth","year":"1973"},{"issue":"6","key":"ref4","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1145\/63526.63532","article-title":"Micropipelines","volume":"32","author":"Sutherland","year":"1989","journal-title":"Commun. ACM"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.21236\/ada447734"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2019.8862081"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027085"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/0166-218X(81)90026-3"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.475126"},{"key":"ref10","first-page":"10","article-title":"Timing analysis of digital circuits and the theory of min-max functions","volume-title":"Proc. ACM\/SIGDA Int. Workshop Timing Issues Specification Synth. Digit. Syst. (TAU)","author":"Gunawardena"},{"key":"ref11","first-page":"189","article-title":"Timing analysis of asynchronous circuits using timed automata","volume-title":"Proc. Adv. Res. Working Conf. Correct Hardw. Design Verification Methods","author":"Pnueli"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2693268"},{"article-title":"A general approach to performance analysis and optimization of asynchronous circuits","year":"1995","author":"Lee","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.31"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2012.27"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/5.740022"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.20"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/BF00935211"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836983"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.114"},{"key":"ref21","first-page":"6","volume-title":"Blame Passing for Analysis and Optimisation","volume":"18","author":"Brej","year":"2007"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/988952.989051"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC49171.2020.00010"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44798-9_12"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00036"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.26"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.111"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3960-5"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/43.205001"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/74382.74475"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/43.62737"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/74382.74476"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/43.406708"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1017\/cbo9780511693014"},{"key":"ref35","first-page":"725","article-title":"Fundamental mode and pulse mode operations of sequential circuits","volume-title":"Proc. IFIP Work. Conf. Design Methodol.","author":"McCluskey"},{"key":"ref36","first-page":"193","article-title":"Automatic synthesis of fast compact self-timed control circuits","volume-title":"Proc. IFIP Work. Conf. Design Methodol.","author":"Coates"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801606"},{"volume-title":"Communication and Concurrency","year":"1989","author":"Milner","key":"ref38"},{"article-title":"Practical verification and synthesis of low latency asynchronous systems","year":"1994","author":"Stevens","key":"ref39"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413183"},{"volume-title":"Introduction to Algorithms","year":"2009","author":"Cormen","key":"ref41"},{"key":"ref42","first-page":"160","article-title":"The post office\u2014Communication support for distributed ensemble architectures","volume-title":"Proc. 6th Int. Conf. Distrib. Comput. Syst.","author":"Stevens"},{"article-title":"Pipelined asynchronous circuits","year":"1998","author":"Lines","key":"ref43"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2010.13"},{"issue":"3","key":"ref45","first-page":"315","article-title":"Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"E80-D","author":"Cortadella","year":"1997","journal-title":"IEICE Trans. Inf. Syst."},{"article-title":"Synthesis of asynchronous controllers for heterogeneous systems","year":"1994","author":"Yun","key":"ref46"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9716240\/09383820.pdf?arnumber=9383820","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,9]],"date-time":"2024-01-09T23:25:05Z","timestamp":1704842705000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9383820\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,3]]},"references-count":46,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3068097","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2022,3]]}}}