{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T08:53:33Z","timestamp":1767084813804,"version":"3.37.3"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,5]]},"DOI":"10.1109\/tcad.2021.3081058","type":"journal-article","created":{"date-parts":[[2021,5,17]],"date-time":"2021-05-17T21:37:11Z","timestamp":1621287431000},"page":"1400-1411","source":"Crossref","is-referenced-by-count":3,"title":["Reducing LUT Count for Mealy FSMs With Transformation of States"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4941-3979","authenticated-orcid":false,"given":"Alexander A.","family":"Barkalov","sequence":"first","affiliation":[{"name":"Institute of Metrology, Electronics and Computer Science, Faculty of Computer, Electrical and Control Engineering, University of Zielona Góra, Zielona Góra, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larysa","family":"Titarenko","sequence":"additional","affiliation":[{"name":"Institute of Metrology, Electronics and Computer Science, Faculty of Computer, Electrical and Control Engineering, University of Zielona Góra, Zielona Góra, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4027-7541","authenticated-orcid":false,"given":"Kamil","family":"Mielcarek","sequence":"additional","affiliation":[{"name":"Institute of Metrology, Electronics and Computer Science, Faculty of Computer, Electrical and Control Engineering, University of Zielona Góra, Zielona Góra, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"issue":"4","key":"ref1","doi-asserted-by":"crossref","first-page":"745","DOI":"10.34768\/amcs-2020-0055","article-title":"Hardware reduction for LUT-based mealy FSMs","volume":"30","author":"Barkalov","year":"2020","journal-title":"Int. J. Appl. Math. Comput. Sci."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0504-8"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1997.617211"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-04708-9"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36166-1"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2692-6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2895206"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1515\/amcs-2017-0015"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858306"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2746749"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2731678"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548558"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2000832.2000835"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1155\/2018\/6831901"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.06.010"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1142\/s0218126615501017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1134\/s106422691302006x"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1134\/s1064230717010129"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45716-X_36"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-38295-7"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.08.001"},{"volume-title":"FPGAs: Instant Access","year":"2008","author":"Maxfield","key":"ref24"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/b978-0-7506-8397-5.x0001-3"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3393-8"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-24202-6"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.2478\/amcs-2018-0046"},{"volume-title":"International Workshop on Logic Synthesis Benchmark Suite (LGSynth93)","year":"1993","key":"ref29"},{"volume-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"De Micheli","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"article-title":"SIS: A system for sequential circuit synthesis","year":"1992","author":"Sentovich","key":"ref32"},{"volume-title":"Design of FPGA-Based Circuits Using Hierarchical Finite State Machines","year":"2012","author":"Skliarova","key":"ref33"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.3390\/computation7040063"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2742-8"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2878187"},{"key":"ref37","first-page":"502","article-title":"FPGA-based decomposition of Boolean functions: Algorithms and implementation","author":"Nowicka","year":"1999","journal-title":"Adv. Comput. Syst."},{"volume-title":"Logic and System Design of Digital Systems","year":"2008","author":"Baranov","key":"ref38"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6155-2"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_76"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1049\/el:20046007"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463760"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.3390\/app10082762"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-59837-6"},{"volume-title":"Synthesis Algorithms for Automata With PLAs","year":"1987","author":"Achasova","key":"ref46"},{"volume-title":"Virtex-7 family overview","year":"2019","key":"ref48"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9760497\/09432403.pdf?arnumber=9432403","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T01:23:35Z","timestamp":1725067415000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9432403\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5]]},"references-count":44,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3081058","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2022,5]]}}}