{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,15]],"date-time":"2026-10-15T16:39:11Z","timestamp":1792082351223,"version":"4.4.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"German Research Foundation (DFG) within the Project VerA","doi-asserted-by":"publisher","award":["GR 3104\/6-1"],"award-info":[{"award-number":["GR 3104\/6-1"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001659","name":"German Research Foundation (DFG) within the Project VerA","doi-asserted-by":"publisher","award":["DR 297\/37-1"],"award-info":[{"award-number":["DR 297\/37-1"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,5]]},"DOI":"10.1109\/tcad.2021.3083682","type":"journal-article","created":{"date-parts":[[2021,5,25]],"date-time":"2021-05-25T19:49:48Z","timestamp":1621972188000},"page":"1573-1586","source":"Crossref","is-referenced-by-count":49,"title":["RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9342-1098","authenticated-orcid":false,"given":"Alireza","family":"Mahzoon","sequence":"first","affiliation":[{"name":"Institute of Computer Science, University of Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1490-6175","authenticated-orcid":false,"given":"Daniel","family":"GroBe","sequence":"additional","affiliation":[{"name":"Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9872-1740","authenticated-orcid":false,"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826548"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1073"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.01.007"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2547898"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/FMCAD.2017.8102237"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772854"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2016.7886676"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2018.00071"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2868362"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218721"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240837"},{"key":"ref13","first-page":"1","article-title":"RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers","volume-title":"Proc. 56th ACM\/IEEE Design Autom. Conf.","author":"Mahzoon"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744925"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10703-018-00329-2"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342263"},{"key":"ref17","first-page":"1048","article-title":"Formal verification of integer multipliers by combining Gr\u00f6bner basis with logic reduction","volume-title":"Proc. Design Autom. Test Eur.","author":"Sayed-Ahmed"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/FMCAD.2019.8894250"},{"key":"ref19","article-title":"Binary adder architectures for cell-based VLSI and their synthesis","author":"Zimmermann","year":"1997"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1201\/9781315275567"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref23","volume-title":"Ideals, Varieties, and Algorithms","author":"Cox","year":"1997"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2912944"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718374"},{"key":"ref26","volume-title":"The EPFL logic synthesis libraries","author":"Soeken","year":"2018"},{"key":"ref27","volume-title":"Arithmetic Module Generator Based on ACG","year":"2019"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-68071-8_9"},{"key":"ref29","volume-title":"ABC: A System for Sequential Synthesis and Verification","year":"2018"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116485"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9760497\/09440537.pdf?arnumber=9440537","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,9]],"date-time":"2024-01-09T23:02:40Z","timestamp":1704841360000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9440537\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5]]},"references-count":30,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3083682","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,5]]}}}