{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,24]],"date-time":"2026-06-24T15:21:00Z","timestamp":1782314460972,"version":"3.54.5"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"EPFL Open Science Fund"},{"DOI":"10.13039\/100000028","name":"SRC","doi-asserted-by":"publisher","award":["2867.001"],"award-info":[{"award-number":["2867.001"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001711","name":"SNF \u201cSupercool: Design methods and tools for superconducting electronics\u201d","doi-asserted-by":"publisher","award":["200021_1920981"],"award-info":[{"award-number":["200021_1920981"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,8]]},"DOI":"10.1109\/tcad.2021.3108704","type":"journal-article","created":{"date-parts":[[2021,8,30]],"date-time":"2021-08-30T21:16:10Z","timestamp":1630358170000},"page":"2573-2586","source":"Crossref","is-referenced-by-count":35,"title":["A Simulation-Guided Paradigm for Logic Synthesis and Verification"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5907-2314","authenticated-orcid":false,"given":"Siang-Yun","family":"Lee","sequence":"first","affiliation":[{"name":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1527-7160","authenticated-orcid":false,"given":"Heinz","family":"Riener","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[{"name":"Department of EECS, University of California at Berkeley, Berkeley, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robert K.","family":"Brayton","sequence":"additional","affiliation":[{"name":"Department of EECS, University of California at Berkeley, Berkeley, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7827-3215","authenticated-orcid":false,"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory, Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.52213"},{"key":"ref2","volume-title":"Synthesis and Optimization of Digital Circuits","author":"De Micheli","year":"1994"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681548"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068720"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715185"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675141"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/0166-218X(84)90081-7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337611"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860955"},{"key":"ref11","first-page":"15","article-title":"Scalable logic synthesis using a simple circuit structure","volume-title":"Proc. IWLS","author":"Mishchenko"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233679"},{"key":"ref13","article-title":"FRAIGs: A unifying representation for logic synthesis and verification","author":"Mishchenko","year":"2005"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207853"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1990.129965"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s00163-010-0097-y"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2017.7934583"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858312"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-81955-1_28"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/800133.804350"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/92.285741"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.264"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123276"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277140"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996691"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.2307\/2963593"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3232195.3232202"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342108"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837401"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/10722167_15"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2997212"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.31"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref39","volume-title":"The EPFL logic synthesis libraries","author":"Soeken","year":"2019"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116310"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9832686\/09524746.pdf?arnumber=9524746","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T23:39:28Z","timestamp":1705016368000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9524746\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8]]},"references-count":40,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3108704","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,8]]}}}