{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,11]],"date-time":"2025-07-11T10:25:12Z","timestamp":1752229512247,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF) grant","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003621","name":"Korea government","doi-asserted-by":"publisher","award":["2019R1A2C3011079"],"award-info":[{"award-number":["2019R1A2C3011079"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,8]]},"DOI":"10.1109\/tcad.2021.3109859","type":"journal-article","created":{"date-parts":[[2021,9,3]],"date-time":"2021-09-03T20:10:21Z","timestamp":1630699821000},"page":"2739-2752","source":"Crossref","is-referenced-by-count":3,"title":["Multibank Optimized Redundancy Analysis Using Efficient Fault Collection"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1177-3853","authenticated-orcid":false,"given":"Hogyeong","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6868-0829","authenticated-orcid":false,"given":"Hayoung","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2385-2375","authenticated-orcid":false,"given":"Donghyun","family":"Han","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7093-2095","authenticated-orcid":false,"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2354381"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294737"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863189"},{"issue":"1","key":"ref4","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"Tarr","year":"1984","journal-title":"Electronics"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.19"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299251"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.28"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.11.0211.0378"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0112.0467"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2760505"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920344"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.simpat.2016.08.008"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2606499"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2017.2778301"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2006.874942"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270266"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/12.73586"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.48"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2007.10"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325273"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1017\/S0021900200013875"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9832686\/09528839.pdf?arnumber=9528839","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T22:41:01Z","timestamp":1705012861000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9528839\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8]]},"references-count":24,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3109859","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2022,8]]}}}