{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T08:25:10Z","timestamp":1773044710821,"version":"3.50.1"},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Open Transprecision Computing (OPRECOM) Project, Summer of Code 2020"},{"name":"Spanish State Research Agency\u2014Ministry of Science and Innovation","award":["PID2019-107255GB"],"award-info":[{"award-number":["PID2019-107255GB"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1109\/tcad.2021.3120073","type":"journal-article","created":{"date-parts":[[2021,10,15]],"date-time":"2021-10-15T14:28:33Z","timestamp":1634308113000},"page":"1663-1673","source":"Crossref","is-referenced-by-count":8,"title":["MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3310-4423","authenticated-orcid":false,"given":"Ismail Emir","family":"Yuksel","sequence":"first","affiliation":[{"name":"Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4043-5044","authenticated-orcid":false,"given":"Behzad","family":"Salami","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oguz","family":"Ergin","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0544-9697","authenticated-orcid":false,"given":"Osman Sabri","family":"Unsal","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian Cristal","family":"Kestelman","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830784"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3018112"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00064"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2020.2989813"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2019.8854386"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.54"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2018.00043"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00039"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSN48063.2020.00032"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2019.8671543"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00023"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.5821\/dissertation-2117-125840"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.32"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00034"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465918"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3084447"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474024"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918284"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2017.117"},{"issue":"1","key":"ref21","first-page":"1","article-title":"Error analysis and retention-aware error management for nand flash memory","volume":"17","author":"Cai","year":"2013","journal-title":"Intel Technol. J."},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2742698"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0849"},{"key":"ref25","volume-title":"FPGA BRAMs Undervolting Study","author":"Salami","year":"2018"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00030"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CAHPC.2018.8645906"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358280"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref30","volume-title":"CUDA-ConvNet","author":"Krizhevsky","year":"2014"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICESS.2019.8782505"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126964"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2010.5450414"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025766"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830811"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00020"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140238"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2015.28"},{"key":"ref39","volume-title":"The MNIST Database of Handwritten Digits","author":"Lecun","year":"1999"},{"key":"ref40","volume-title":"The CIFAR-10 Dataset","author":"Krizhevsky","year":"2009"},{"key":"ref41","first-page":"1","article-title":"Incremental network quantization: Towards lossless CNNs with low-precision weights","volume-title":"Proc. ICLR","author":"Zhou"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080221"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00016"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.521"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465834"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref48","volume-title":"ADaPTION: Toolbox and benchmark for training convolutional neural networks with reduced numerical precision weights and activation","author":"Milde","year":"2017"},{"key":"ref49","volume-title":"NVIDIA-Caffe Extension","year":"2017"},{"key":"ref50","volume-title":"Mixed precision training","author":"Micikevicius","year":"2017"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00091"},{"key":"ref52","volume-title":"T-BFA: Targeted bit-flip adversarial weight attack","author":"Rakin","year":"2021"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00130"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203770"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951802"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2012.6283014"},{"key":"ref57","article-title":"Bit error robustness for energy-efficient DNN accelerators","volume-title":"Proc. Mach. Learn. Syst.","volume":"3","author":"Stutz"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062292"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/PDP50117.2020.00023"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9778249\/09570819.pdf?arnumber=9570819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T00:07:47Z","timestamp":1705018067000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9570819\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6]]},"references-count":59,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3120073","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6]]}}}