{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,29]],"date-time":"2025-08-29T10:49:15Z","timestamp":1756464555016,"version":"3.37.3"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation Awards","doi-asserted-by":"publisher","award":["CCF-1755825","CNS-1908471","CCF-1822976","CCF-2113307"],"award-info":[{"award-number":["CCF-1755825","CNS-1908471","CCF-1822976","CCF-2113307"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency Cooperative Agreement","doi-asserted-by":"publisher","award":["HR00112020002"],"award-info":[{"award-number":["HR00112020002"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000006","name":"Office of Naval Research","doi-asserted-by":"publisher","award":["N000142112332"],"award-info":[{"award-number":["N000142112332"]}],"id":[{"id":"10.13039\/100000006","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,11]]},"DOI":"10.1109\/tcad.2021.3138356","type":"journal-article","created":{"date-parts":[[2021,12,24]],"date-time":"2021-12-24T20:30:20Z","timestamp":1640377820000},"page":"4600-4611","source":"Crossref","is-referenced-by-count":4,"title":["COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8522-4617","authenticated-orcid":false,"given":"Sven","family":"Thijssen","sequence":"first","affiliation":[{"name":"Department of Computer Science, University of Central Florida, Orlando, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0354-2940","authenticated-orcid":false,"given":"Sumit Kumar","family":"Jha","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Texas at San Antonio, San Antonio, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4183-6926","authenticated-orcid":false,"given":"Rickard","family":"Ewetz","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/85.238389"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"volume-title":"Computation of boolean formulas using sneak paths in crossbar computing","year":"2016","author":"Jha","key":"ref7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482461"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6271792"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-13-8379-3_8"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038603"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2933774"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357090"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538936"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180599"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927093"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2821678"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2017.8123643"},{"key":"ref19","first-page":"1","article-title":"Free BDD based CAD of compact memristor crossbars for in-memory computing","volume-title":"Proc. IEEE\/ACM Int. Symp. Nanoscale Architect. (NANOARCH)","author":"Hassen"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114828"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.0906949106"},{"key":"ref25","volume-title":"Introduction to Graph Theory","volume":"2","author":"West","year":"1996"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-21275-3"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/springerreference_57547"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-2001-2_9"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-56939-1_60"},{"volume-title":"20.1 IBM ILOG CPLEX Optimization Studio CPLEX User\u2019s Manual","year":"2020","key":"ref30"},{"key":"ref31","first-page":"695","article-title":"Accelerated atpg and fault grading via testability analysis","volume-title":"Proc. IEEE Int. Symp. Circuits Syst.","author":"Brglez"},{"article-title":"The EPFL combinational benchmark suite","volume-title":"Proc. 24th Int. Workshop Logic Synthesis (IWLS)","author":"Amar\u00fa","key":"ref32"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2013.6706773"},{"key":"ref34","first-page":"1","article-title":"Contra: Area-constrained technology mapping framework for memristive memory processing unit","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Bhattacharjee"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9928799\/9662445-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9928799\/09662445.pdf?arnumber=9662445","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T00:05:30Z","timestamp":1704845130000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9662445\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11]]},"references-count":34,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2021.3138356","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2022,11]]}}}