{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T19:02:46Z","timestamp":1773774166536,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"German Research Council (DFG) through the DART-HMS Project","doi-asserted-by":"publisher","award":["437232907"],"award-info":[{"award-number":["437232907"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001659","name":"TraceSymm Project","doi-asserted-by":"publisher","award":["366764507"],"award-info":[{"award-number":["366764507"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,12]]},"DOI":"10.1109\/tcad.2022.3161198","type":"journal-article","created":{"date-parts":[[2022,3,22]],"date-time":"2022-03-22T19:44:52Z","timestamp":1647978292000},"page":"5288-5298","source":"Crossref","is-referenced-by-count":4,"title":["BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2763-8755","authenticated-orcid":false,"given":"Fazal","family":"Hameed","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Institute of Space Technology, Islamabad, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5007-445X","authenticated-orcid":false,"given":"Jeronimo","family":"Castrillon","sequence":"additional","affiliation":[{"name":"Chair for Compiler Construction and the Center for Advancing Electronics Dresden, Technische Universität Dresden, Dresden, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/2.16187"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2019.00037"},{"key":"ref31","first-page":"1","article-title":"Accelerating graph computation with racetrack memory and pointer-assisted graph representation","author":"park","year":"2014","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2902967"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ITW.2018.8613352"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2018.2807480"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.30"},{"key":"ref13","first-page":"23","article-title":"A case for (partially) tagged geometric history length branch prediction","volume":"8","author":"seznec","year":"2006","journal-title":"J Instruction Level Parallelism"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919638"},{"key":"ref16","year":"2021","journal-title":"Standard Performance Evaluation Corporation"},{"key":"ref17","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program analysis","volume":"7","author":"hamerly","year":"2005","journal-title":"J Instruction Level Parallelism"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2131610"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627651"},{"key":"ref4","first-page":"417","article-title":"Multilane racetrack caches: Improving efficiency through compression and independent shifting","author":"xu","year":"2015","journal-title":"Proc Asia South Pac Des Autom Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627643"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506581"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2360545"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744826"},{"key":"ref5","first-page":"100","article-title":"Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power","author":"zhang","year":"2015","journal-title":"Proc Asia South Pac Des Autom Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.41"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1121"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2536020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2975719"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333707"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea7030023"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324558"},{"key":"ref21","first-page":"1","article-title":"Exploration of GPGPU register file architecture using domain-wall-shift-write based racetrack memory","author":"mao","year":"2014","journal-title":"Proc 51st Annu Des Autom Conf Des Autom Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3316482.3326351"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2397876"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3372489"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NVMSA.2015.7304358"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9956950\/09739802.pdf?arnumber=9739802","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,12]],"date-time":"2022-12-12T19:41:24Z","timestamp":1670874084000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9739802\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12]]},"references-count":33,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2022.3161198","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12]]}}}