{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T18:41:38Z","timestamp":1775068898040,"version":"3.50.1"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Shandong Provincial Key Technology Innovation Project","award":["2019JZZY010203"],"award-info":[{"award-number":["2019JZZY010203"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,12]]},"DOI":"10.1109\/tcad.2022.3166637","type":"journal-article","created":{"date-parts":[[2022,4,12]],"date-time":"2022-04-12T19:34:26Z","timestamp":1649792066000},"page":"5182-5192","source":"Crossref","is-referenced-by-count":56,"title":["An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7454-245X","authenticated-orcid":false,"given":"Ranran","family":"Zhou","sequence":"first","affiliation":[{"name":"School of Microelectronics, Shandong University, Jinan, China"}]},{"given":"Peter","family":"Poechmueller","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Shandong University, Jinan, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6063-5767","authenticated-orcid":false,"given":"Yong","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Shandong University, Jinan, China"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCES51560.2020.9334576"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907284"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.806600"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2961322"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.820897"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2661804"},{"key":"ref36","first-page":"1101","article-title":"Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model","author":"liu","year":"2011","journal-title":"Proc Design Autom Test Europe"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2873953"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2004.1399700"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729461"},{"key":"ref27","first-page":"398","article-title":"Use of particle swarm optimization to design combinational logic circuits","author":"coello coello","year":"2003","journal-title":"Proc Int Conf Evol Syst"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828130"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882513"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2681062"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008306431147"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.102664"},{"key":"ref24","first-page":"267","article-title":"Technology migration of analogue CMOS circuits using Hooke&#x2013;Jeeves algorithm and genetic algorithms in multi-core CPU systems","author":"naumowicz","year":"2013","journal-title":"Proc Int Conf Mixed Design Integr Circuits Syst (MIXDES'06)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008202821328"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/s10845-008-0140-2"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-009-9361-3"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.895520"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2848590"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942046"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2007.911969"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.806606"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2053151"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2162067"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.992763"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828135"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2234826"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2859242"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/43.848091"},{"key":"ref4","article-title":"An efficient analog circuit sizing method based on machine learning assisted global optimization","author":"budak","year":"2021","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3054811"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052861"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2681062"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807410"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2376987"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.04.010"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.826209"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.2307\/2291282"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2993059"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/4.826814"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2939336"},{"key":"ref41","article-title":"LoCoMOBO: A local constrained multi-objective Bayesian optimization for analog circuit sizing","author":"touloupas","year":"2021","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/74.382334"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2442260"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9956950\/09756017.pdf?arnumber=9756017","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,12]],"date-time":"2022-12-12T19:42:59Z","timestamp":1670874179000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9756017\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12]]},"references-count":50,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2022.3166637","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12]]}}}