{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T16:15:30Z","timestamp":1762272930709,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1651701"],"award-info":[{"award-number":["1651701"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2022,12]]},"DOI":"10.1109\/tcad.2022.3166675","type":"journal-article","created":{"date-parts":[[2022,4,12]],"date-time":"2022-04-12T19:34:26Z","timestamp":1649792066000},"page":"5207-5219","source":"Crossref","is-referenced-by-count":7,"title":["EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1837-1622","authenticated-orcid":false,"given":"Sarah","family":"Amir","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2794-7320","authenticated-orcid":false,"given":"Domenic","family":"Forte","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"2004","key":"ref30"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228378"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0001-6"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-018-0036-3"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PACET48583.2019.8956251"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"ref15","article-title":"GNNUnlock: Graph neural networks-based oracle-less unlocking scheme for provably secure logic locking","author":"alrahis","year":"2020","journal-title":"arXiv 2012 05948"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49445-6_1"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415648"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref19","first-page":"136","article-title":"Towards an extension of rent’s rule for describing local variations in interconnection complexity","author":"van marck","year":"1995","journal-title":"Proc 4th Int Conf Young Comput Sci"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084687"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2188769"},{"key":"ref27","article-title":"A tutorial on principal component analysis","author":"shlens","year":"2014","journal-title":"arXiv 1404 1100"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-15334-2"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"journal-title":"TetraMAX R ATPG User Guide Version X-2005","first-page":"249","year":"2005","key":"ref29"},{"key":"ref5","first-page":"677","article-title":"A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran","author":"brglez","year":"1985","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/6.591665"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"265","DOI":"10.1145\/127601.127678","article-title":"Benchmarks for layout synthesis - evolution and current status","author":"kozminski","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49019-9"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657085"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"ref20","first-page":"94","article-title":"Characterization and parameterized random generation of digital circuits","author":"hutton","year":"1996","journal-title":"Proc 33rd Annu Conf Des Autom"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.728919"},{"journal-title":"Clustered And Iterative Synthetic Circuit Generation","year":"2003","author":"hutton","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176634"},{"journal-title":"Trust-Hub Website","year":"2017","key":"ref23"},{"journal-title":"Pattern Recognition and Machine Learning","year":"2006","author":"bishop","key":"ref26"},{"key":"ref25","volume":"2","author":"luenberger","year":"1984","journal-title":"Linear and Nonlinear Programming"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/9956950\/9755987-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9956950\/09755987.pdf?arnumber=9755987","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,12]],"date-time":"2022-12-12T19:41:39Z","timestamp":1670874099000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9755987\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12]]},"references-count":32,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2022.3166675","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2022,12]]}}}