{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T01:15:00Z","timestamp":1773018900499,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Taiwan MOST","award":["NSTC 111-2221-E-A49-137-MY3"],"award-info":[{"award-number":["NSTC 111-2221-E-A49-137-MY3"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1109\/tcad.2022.3199307","type":"journal-article","created":{"date-parts":[[2022,8,15]],"date-time":"2022-08-15T19:54:28Z","timestamp":1660593268000},"page":"1268-1279","source":"Crossref","is-referenced-by-count":4,"title":["On Reducing LDE Variations in Modern Analog Placement"],"prefix":"10.1109","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7923-0807","authenticated-orcid":false,"given":"A. K.","family":"Thasreefa","sequence":"first","affiliation":[{"name":"Test Chip Methodology, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7094-7601","authenticated-orcid":false,"given":"Abhishek","family":"Patyal","sequence":"additional","affiliation":[{"name":"Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan"}]},{"given":"Hao-Yu","family":"Chi","sequence":"additional","affiliation":[{"name":"Systems Design Group, Synopsys Taiwan Company Ltd., Hsinchu, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2292-2308","authenticated-orcid":false,"given":"Mark Po-Hung","family":"Lin","sequence":"additional","affiliation":[{"name":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8173-3131","authenticated-orcid":false,"given":"Hung-Ming","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391484"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"791","DOI":"10.1109\/TCAD.2009.2017433","article-title":"Analog placement based on symmetry-island formulation","volume":"28","author":"lin","year":"2009","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320869"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923083"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.552084"},{"key":"ref2","first-page":"464","article-title":"CMOS opamp circuit synthesis with geometric programming models for layout-dependent effects","author":"zhang","year":"2012","journal-title":"Proc IEEE Int Symp Qual Electron Design (ISQED)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617407"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870076"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.engappai.2020.104102"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2019.8795297"},{"key":"ref9","year":"0","journal-title":"BSIM4 50"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2556750"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2015.7440354"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2501293"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2883710"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10077488\/09858091.pdf?arnumber=9858091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,4,10]],"date-time":"2023-04-10T19:16:22Z","timestamp":1681154182000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9858091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":16,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2022.3199307","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4]]}}}