{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T16:15:48Z","timestamp":1775837748858,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100012282","name":"Beijing Innovation Center for Future Chips","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012282","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Tsinghua\u2013Meituan Joint Institute for Digital Life"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2023,11]]},"DOI":"10.1109\/tcad.2023.3251696","type":"journal-article","created":{"date-parts":[[2023,3,2]],"date-time":"2023-03-02T18:24:21Z","timestamp":1677781461000},"page":"4112-4125","source":"Crossref","is-referenced-by-count":53,"title":["MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures"],"prefix":"10.1109","volume":"42","author":[{"given":"Zhenhua","family":"Zhu","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]},{"given":"Hanbo","family":"Sun","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]},{"given":"Tongxin","family":"Xie","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]},{"given":"Yu","family":"Zhu","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8464-0130","authenticated-orcid":false,"given":"Guohao","family":"Dai","sequence":"additional","affiliation":[{"name":"Qing Yuan Research Institute, Shanghai Jiao Tong University, Shanghai, China"}]},{"given":"Lixue","family":"Xia","sequence":"additional","affiliation":[{"name":"Department of Cloud Intelligence, Alibaba Group, Beijing, China"}]},{"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[{"name":"Computing Technology Laboratory, Alibaba DAMO Academy, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7337-1844","authenticated-orcid":false,"given":"Xiaoming","family":"Chen","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6636-9738","authenticated-orcid":false,"given":"Xiaobo Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6968-1180","authenticated-orcid":false,"given":"Yu","family":"Cao","sequence":"additional","affiliation":[{"name":"School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, USA"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Computing Technology Laboratory, Alibaba DAMO Academy, Hangzhou, China"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6108-5157","authenticated-orcid":false,"given":"Yu","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317870"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050624"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240800"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418106"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3323439.3323989"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774605"},{"key":"ref14","first-page":"1","article-title":"Design guidelines of RRAM based neural-processingunit: A joint device-circuit-algorithm analysis","author":"zhang","year":"2019","journal-title":"Proc 56th ACM\/IEEE Design Autom Conf (DAC)"},{"key":"ref36","first-page":"1","article-title":"Comparative study of sense amplifiers for SRAM","volume":"4","author":"shafique","year":"2016","journal-title":"Int J Eng Res Technol"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1063\/1.5037896"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref11","first-page":"1009","article-title":"MNSIM: Simulation platform for memristor-based neuromorphic computing system","volume":"37","author":"xia","year":"2018","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502370"},{"key":"ref10","first-page":"188","article-title":"A 1.041-Mb\/mm2 27.38-TOPS\/W signed-INT8 dynamiclogic- based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and embedded applications","volume":"65","author":"yan","year":"2022","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870467"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCVW.2015.58"},{"key":"ref1","first-page":"91","article-title":"Faster R-CNN: Towards realtime object detection with region proposal networks","volume":"28","author":"ren","year":"2015","journal-title":"Proc Int Conf Adv Neural Inf Process Syst"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3160947"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.02.002"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317739"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045192"},{"key":"ref20","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3358176"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2020.3001559"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062953"},{"key":"ref29","year":"2014","journal-title":"CIFAR-10—Object Recognition in Images Kaggle"},{"key":"ref8","first-page":"238","article-title":"15.2 A 2.75-to-75.9TOPS\/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and pingpong CIM with simultaneous computation and weight updating","volume":"64","author":"yue","year":"2021","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-020-1942-4"},{"key":"ref9","first-page":"252","article-title":"16.4 An 89TOPS\/W and 16.3TOPS\/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications","volume":"64","author":"chi","year":"2021","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2882603"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10288105\/10058114.pdf?arnumber=10058114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,8]],"date-time":"2023-11-08T19:03:11Z","timestamp":1699470191000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10058114\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11]]},"references-count":37,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3251696","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,11]]}}}