{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:20Z","timestamp":1780674740242,"version":"3.54.1"},"reference-count":159,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,12,1]],"date-time":"2023-12-01T00:00:00Z","timestamp":1701388800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006785","name":"Google Security and Privacy Research Award","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006785","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004318","name":"Microsoft Swiss Joint Research Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004318","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2023,12]]},"DOI":"10.1109\/tcad.2023.3282172","type":"journal-article","created":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T17:31:54Z","timestamp":1685640714000},"page":"5098-5112","source":"Crossref","is-referenced-by-count":43,"title":["DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips"],"prefix":"10.1109","volume":"42","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5333-5726","authenticated-orcid":false,"given":"Ataberk","family":"Olgun","sequence":"first","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hasan","family":"Hassan","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A. Giray","family":"Ya\u011fl\u0131k\u00e7\u0131","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9291-3626","authenticated-orcid":false,"given":"Yahya Can","family":"Tu\u011frul","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6773-6395","authenticated-orcid":false,"given":"Lois","family":"Orosa","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haocong","family":"Luo","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7725-4792","authenticated-orcid":false,"given":"Minesh","family":"Patel","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"O\u011fuz","family":"Ergin","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Türkiye"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Department of D-ITET, ETH Zurich, Zurich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"V6000 memory platform","year":"2023"},{"key":"ref2","volume-title":"LiteX row hammer tester\u2014GitHub repository","year":"2023"},{"key":"ref3","volume-title":"Why is EtherBone bridge so slow?","year":"2023"},{"key":"ref4","volume-title":"AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite","year":"2013"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872390"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2019.8662060"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699247"},{"key":"ref8","volume-title":"Bittware XUPP3R FPGA board","year":"2023"},{"key":"ref9","volume-title":"Bittware XUPVVH FPGA board","year":"2023"},{"key":"ref10","volume-title":"Bittware XUSP3S FPGA board","year":"2023"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337162"},{"key":"ref12","volume-title":"DRAMPower: Open-source DRAM power & energy estimation tool","author":"Chandrasekar","year":"2023"},{"key":"ref13","article-title":"Understanding and improving the latency of DRAM-based memory systems","author":"Chang","year":"2017"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2964791.2901453"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835946"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3143314.3078590"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750402"},{"key":"ref19","volume-title":"Field-effect transistor memory","author":"Dennard","year":"1968"},{"key":"ref20","volume-title":"DFI 5.0 Specification","year":"2018"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00090"},{"key":"ref22","volume-title":"FS2800 DDR detective","year":"2023"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2931347"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3292040.3219661"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/access.2022.3174101"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/16.678551"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322231"},{"key":"ref31","article-title":"A case for self-managing DRAM chips: Improving performance, efficiency, reliability, and security via autonomous in-DRAM maintenance operations","author":"Hassan","year":"2022","journal-title":"arXiv:2207.13358"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446096"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480110"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/vldi-dat.2013.6533853"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893602"},{"key":"ref37","volume-title":"Functional Description\u2014RLDRAM 3 PHY-Only IP","year":"2014"},{"key":"ref38","volume-title":"External Memory Interface Handbook Volume 3: Reference Material","year":"2019"},{"key":"ref39","volume-title":"Multi Channel DMA Intel FPGA IP for PCI Express User Guide","year":"2022"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382172"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04478-0"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2815631"},{"key":"ref43","volume-title":"Low Power Double Data Rate 2 (LPDDR2)","year":"2011"},{"key":"ref44","volume-title":"JESD79-3: DDR3 SDRAM Standard","year":"2012"},{"key":"ref45","volume-title":"Low Power Double Data Rate 3 (LPDDR3)","year":"2013"},{"key":"ref46","volume-title":"JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard","year":"2017"},{"key":"ref47","volume-title":"JESD209-5A: LPDDR5 SDRAM Standard","year":"2020"},{"key":"ref48","volume-title":"JESD79-4C: DDR4 SDRAM Standard","year":"2020"},{"key":"ref49","volume-title":"JESD79-5: DDR5 SDRAM Standard","year":"2020"},{"key":"ref50","volume-title":"JESD235D: High Bandwidth Memory DRAM (HBM1, HBM2)","year":"2021"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2967217"},{"key":"ref52","first-page":"4","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","volume-title":"Proc. Memory Forum","author":"Kang"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544426"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2015.7138756"},{"key":"ref55","volume-title":"34134A AC\/DC DMM current probe user manual","year":"2023"},{"key":"ref56","volume-title":"Keysight truevolt series DMM operating and service guide","year":"2023"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/2637364.2592000"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2624298"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00051"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00026"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00011"},{"key":"ref64","first-page":"638","article-title":"Revisiting RowHammer: An experimental analysis of modern devices and mitigation techniques","volume-title":"Proc. ISCA","author":"Kim"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665726"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2010.5416658"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358280"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00020"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/3143314.3078533"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2013.6522354"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2787674"},{"key":"ref75","volume-title":"Payload executor ISA considerations","year":"2023"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485928"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589063"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00061"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSNT50940.2020.9304999"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0187"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507702"},{"key":"ref83","volume-title":"FT20X user manual","year":"2023"},{"key":"ref84","volume-title":"JET-5612A straight DDR4 DIMM extender","year":"2023"},{"key":"ref85","volume-title":"Mobile LPDDR3 SDRAM","year":"2023"},{"key":"ref86","volume-title":"Hybrid Memory Cube\u2014HMC Gen2","year":"2018"},{"key":"ref87","volume-title":"TN-41-01: Calculating Memory System Power for DDR3","year":"2007"},{"key":"ref88","volume-title":"TN-40-07: Calculating memory power for DDR4 SDRAM","year":"2017"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774614"},{"key":"ref90","first-page":"1","article-title":"Memory performance attacks: Denial of memory service in multi-core systems","volume-title":"Proc. USENIX Security","author":"Moscibroda"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927156"},{"key":"ref93","volume-title":"RowHammer","author":"Mutlu","year":"2018"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-16-7487-7_7"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915318"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3568350"},{"key":"ref99","volume-title":"DRAM memory testing","year":"2022"},{"key":"ref100","article-title":"Sectored DRAM: An energy-efficient high-throughput and practical fine-grained DRAM architecture","author":"Olgun","year":"2022","journal-title":"arXiv:2207.13795"},{"key":"ref101","article-title":"DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips","author":"Olgun","year":"2022","journal-title":"arXiv:2211.05838"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1145\/3563697"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-S58398.2023.00042"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00078"},{"key":"ref105","article-title":"SpyHammer: Using RowHammer to remotely spy on temperature","author":"Orosa","year":"2022","journal-title":"arXiv:2210.04084"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00045"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480069"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00014"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00034"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2019.00017"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080242"},{"key":"ref112","volume-title":"PCI Express Base Specification Revision 3.0","year":"2010"},{"key":"ref113","volume-title":"Pybind11\u2014GitHub repository","year":"2022"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035340"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2445053"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref117","volume-title":"RS PRO type K thermocouple","year":"2023"},{"key":"ref118","volume-title":"DRAM-bender\u2014GitHub repository","year":"2023"},{"key":"ref119","volume-title":"QUAC-TRNG\u2014GitHub repository","year":"2023"},{"key":"ref120","volume-title":"U-TRR\u2014GitHub repository","year":"2023"},{"key":"ref121","volume-title":"SoftMC\u2014GitHub repository","year":"2023"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507716"},{"key":"ref123","first-page":"1","article-title":"Exploiting the DRAM Rowhammer bug to gain kernel privileges","volume-title":"Proc. Black Hat","author":"Seaborn"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"ref128","article-title":"In-DRAM bulk bitwise execution engine","author":"Seshadri","year":"2019","journal-title":"arXiv:1905.09822"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062281"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485955"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974655"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1145\/3105915"},{"key":"ref133","volume-title":"Magnum memory test system","year":"2023"},{"key":"ref134","volume-title":"Pandas","year":"2020"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978406"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/hpca.2006.1598122"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3060362"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00032"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00036"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.21105\/joss.03021"},{"key":"ref142","volume-title":"Virtex-6 FPGA memory interface solutions","year":"2023"},{"key":"ref143","volume-title":"Xilinx Zynq-7000 SoC ZC706 evaluation kit","year":"2023"},{"key":"ref144","volume-title":"7 Series FPGAs Memory Interface Solutions","year":"2011"},{"key":"ref145","volume-title":"ML605 Hardware User Guide","year":"2012"},{"key":"ref146","volume-title":"ISE Design Suite 14: Release Notes, Installation, and Licensing","year":"2020"},{"key":"ref147","volume-title":"Vivado Design Suite User Guide: Logic Simulation","year":"2020"},{"key":"ref148","volume-title":"AXI High Bandwidth Memory Controller V1.0","year":"2021"},{"key":"ref149","volume-title":"DMA\/Bridge Subsystem for PCI Express V4.1","year":"2021"},{"key":"ref150","volume-title":"UltraScale Architecture-Based FPGAs Memory IP V1.4","year":"2021"},{"key":"ref151","volume-title":"Xilinx Alveo U200 FPGA board","year":"2023"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1109\/DSN53405.2022.00054"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00062"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00037"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2015.7114502"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317866"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052325"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1145\/3409114"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665724"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10325328\/10141996.pdf?arnumber=10141996","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,12]],"date-time":"2024-03-12T18:47:40Z","timestamp":1710269260000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10141996\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,12]]},"references-count":159,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3282172","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,12]]}}}