{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T16:21:11Z","timestamp":1781713271602,"version":"3.54.5"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Key Research and Development Program Projects of the Ministry of Science and Technology","award":["2021ZD0114702"],"award-info":[{"award-number":["2021ZD0114702"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2024,2]]},"DOI":"10.1109\/tcad.2023.3313101","type":"journal-article","created":{"date-parts":[[2023,9,7]],"date-time":"2023-09-07T17:34:32Z","timestamp":1694108072000},"page":"641-653","source":"Crossref","is-referenced-by-count":7,"title":["Multielectrostatic FPGA Placement Considering SLICEL\u2013SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization"],"prefix":"10.1109","volume":"43","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3787-1534","authenticated-orcid":false,"given":"Jing","family":"Mai","sequence":"first","affiliation":[{"name":"School of Computer Science, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7054-384X","authenticated-orcid":false,"given":"Jiarui","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Computer Science, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7323-5052","authenticated-orcid":false,"given":"Zhixiong","family":"Di","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2008.4564891"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2478963"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842812"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744903"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729349"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980084"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980085"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2877017"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3174849"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293897"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203880"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643574"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3053191"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2968892"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2886419"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3038241"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691130"},{"key":"ref18","volume-title":"Ultrascale architecture clocking resources","year":"2023"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317743"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474054"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"ref22","volume-title":"Field programmable gate arrays using semi-hard multicell macros","author":"Fuller","year":"1998"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.17"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044116"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.317462"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/1-4020-8063-8_5"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2778058"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3233244"},{"key":"ref29","volume-title":"Ultrascale Architecture CLB Slices","year":"2023"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2699873"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317803"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2391263"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505423"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1137\/060654797"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530568"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567898"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296428"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372666"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003843"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10410112\/10242369.pdf?arnumber=10242369","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T04:55:31Z","timestamp":1706072131000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10242369\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,2]]},"references-count":40,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3313101","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,2]]}}}