{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T12:54:34Z","timestamp":1760014474757,"version":"3.37.3"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,3,1]],"date-time":"2024-03-01T00:00:00Z","timestamp":1709251200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62172387"],"award-info":[{"award-number":["62172387"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002367","name":"Youth Innovation Promotion Association of Chinese Academy of Sciences","doi-asserted-by":"publisher","award":["2021098"],"award-info":[{"award-number":["2021098"]}],"id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2024,3]]},"DOI":"10.1109\/tcad.2023.3329778","type":"journal-article","created":{"date-parts":[[2023,11,6]],"date-time":"2023-11-06T19:26:15Z","timestamp":1699298775000},"page":"878-891","source":"Crossref","is-referenced-by-count":3,"title":["Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration"],"prefix":"10.1109","volume":"43","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8819-904X","authenticated-orcid":false,"given":"Hongyan","family":"Li","sequence":"first","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6233-3538","authenticated-orcid":false,"given":"Hang","family":"Lu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, the Zhongguancun Laboratory, and the Shanghai Innovation Center for Processor Technologies, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0874-814X","authenticated-orcid":false,"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2019.00972"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-018-01144-2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-27413-8_47"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080246"},{"volume-title":"Flickr image dataset","year":"2023","key":"ref5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366056"},{"volume-title":"Enflame DTU","year":"2023","author":"Technology","key":"ref7"},{"volume-title":"CambriconMLU290","year":"2023","key":"ref8"},{"key":"ref9","article-title":"Exploring the potential of low-bit training of convolutional neural networks","author":"Zhong","year":"2020","journal-title":"arXiv:2006.02804"},{"key":"ref10","first-page":"1","article-title":"Shifted and squeezed 8-bit floating point format for low-precision training of deep neural networks","volume-title":"Proc. ICLR","author":"Cambier"},{"key":"ref11","first-page":"1","article-title":"Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks","volume-title":"Proc. NIPS","author":"Sun"},{"key":"ref12","first-page":"1","article-title":"Mixed precision training with 8-bit floating point","volume-title":"Proc. ICLR","author":"Mellempudi"},{"key":"ref13","article-title":"FP8 formats for deep learning","author":"Micikevicius","year":"2022","journal-title":"arXiv:2209.05433"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3472456.3472513"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123982"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567868"},{"key":"ref17","first-page":"1","article-title":"BinaryConnect: Training deep neural networks with binary weights during propagations","volume-title":"Proc. NIPS","author":"Courbariaux"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref19","first-page":"2704","article-title":"Quantization and training of neural networks for efficient integer-arithmetic-only inference","volume-title":"Proc. CVPR","author":"Jacob"},{"key":"ref20","article-title":"Convolutional neural networks using logarithmic data representation","author":"Miyashita","year":"2016","journal-title":"arXiv:1603.01025"},{"volume-title":"IEEE standard for floating-point arithmetic (754-2019)","year":"2019","key":"ref21"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240855"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322255"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731762"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480123"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"volume-title":"Pytorch","year":"2023","key":"ref27"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.634"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2010.11929"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/LSP.2020.3013518"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1804.02767"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10602-1_48"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.8.63"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.618"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00986"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783722"},{"key":"ref39","first-page":"1","article-title":"SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size","volume-title":"Proc. ICLR","author":"Iandola"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3222059"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492476"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10440374\/10309853.pdf?arnumber=10309853","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,12]],"date-time":"2024-12-12T19:14:55Z","timestamp":1734030895000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10309853\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,3]]},"references-count":41,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3329778","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2024,3]]}}}