{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:51Z","timestamp":1780674771857,"version":"3.54.1"},"reference-count":66,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1109\/tcad.2023.3333290","type":"journal-article","created":{"date-parts":[[2023,11,15]],"date-time":"2023-11-15T18:59:02Z","timestamp":1700074742000},"page":"1191-1205","source":"Crossref","is-referenced-by-count":15,"title":["Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros"],"prefix":"10.1109","volume":"43","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5337-5680","authenticated-orcid":false,"given":"Xiaoyu","family":"Sun","sequence":"first","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weidong","family":"Cao","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Brian","family":"Crafton","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5957-826X","authenticated-orcid":false,"given":"Kerem","family":"Akarvardar","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haruki","family":"Mori","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hidehiro","family":"Fujiwara","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hiroki","family":"Noguchi","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yih","family":"Wang","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tsung-Yung Jonathan","family":"Chang","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1512.02325"},{"key":"ref3","article-title":"BERT: Pre-training of deep bidirectional transformers for language understanding","author":"Devlin","year":"2018","journal-title":"arXiv:1810.04805"},{"key":"ref4","first-page":"1135","article-title":"Learning both weights and connections for efficient neural network","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Han"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.521"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080246"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00010"},{"key":"ref8","first-page":"1","article-title":"A 5-nm 254-TOPS\/W 221-TOPS\/mm 2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage-frequency scaling and simultaneous MAC and write operations","volume-title":"Proc. IEEE ISSCC","author":"Fujiwara"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062985"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3164651"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"},{"key":"ref13","first-page":"1","article-title":"A 40nm 64kb 26.56TOPS\/W 2.37Mb\/mm2RRAM binary\/compute-in-memory macro with 4.23x improvement in density and use of sensing dynamic range","volume-title":"Proc. IEEE ISSCC","author":"Spetalnick"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731621"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731670"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731775"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3078541"},{"key":"ref18","first-page":"352","article-title":"MLPerf mobile inference benchmark: An industry-standard open-source machine learning benchmark for on-device AI","volume-title":"Proc. Mach. Learn. Syst.","author":"Reddi"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS48437.2020.00016"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830211"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3211290"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365984"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067527"},{"key":"ref25","first-page":"252","article-title":"An 89tops\/w and 16.3 tops\/mm 2 all-digital sram-based full-precision compute-in memory macro in 22nm for machine-learning edge applications","volume-title":"Proc. IEEE ISSCC","author":"Chih"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830438"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2933148"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731762"},{"key":"ref29","first-page":"132","article-title":"A 4nm 6163-TOPS\/W\/b-4790-TOPS\/mm2 SRAM based digital-computing-in-memory macro supporting bit-width flexibility and simultaneous MAC and weight update","volume-title":"Proc. IEEE ISSCC","author":"Mori"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2974843"},{"key":"ref31","volume-title":"Introducing the next generation of on-device vision models: MobileNetV3 and MobileNetEdgeTPU","author":"Howard","year":"2019"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR46437.2021.00382"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1802.02611"},{"key":"ref34","article-title":"MOSAIC: Mobile segmentation via decoding aggregated information and encoded context","author":"Wang","year":"2021","journal-title":"arXiv:2112.11623"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/2020.acl-main.195"},{"key":"ref36","first-page":"841","article-title":"NeuroMeter: An integrated power, area, and timing modeling framework for machine learning accelerators","volume-title":"Proc. IEEE HPCA","author":"Tang"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712598"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218567"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.544"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2938396"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2976475"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173176"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/3117811.3117815"},{"key":"ref45","first-page":"266","article-title":"DIMC: 2219 TOPS\/W 2569 F2\/b digital in-memory computing macro in 28nm based on approximate arithmetic hardware","volume-title":"Proc. IEEE ISSCC","author":"Wang"},{"key":"ref46","first-page":"1","article-title":"A 40nm 60.64 TOPS\/W ECC-capable compute-in-memory\/digital 2.25 MB\/768KB RRAM\/SRAM system with embedded cortex M3 microprocessor for edge recommendation systems","volume-title":"Proc. IEEE ISSCC","author":"Chang"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365788"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365989"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366045"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365958"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067260"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067779"},{"key":"ref53","first-page":"466","article-title":"A 28nm 15.59 \u03bcJ\/token full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline\/parallel reconfigurable modes","volume-title":"Proc. IEEE ISSCC","author":"Tu"},{"key":"ref54","first-page":"248","article-title":"MuITCIM: A 28nm 2.24 \u03bcJ \/token attention-token-bit hybrid sparse digital CIM-based accelerator for multimodal transformers","volume-title":"Proc. IEEE ISSCC","author":"Tu"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067360"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00029"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3129647"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473985"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067526"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00015"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.29"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC53511.2021.00028"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00096"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1145\/3424669"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS48437.2020.00024"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10477239\/10318181.pdf?arnumber=10318181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T19:40:21Z","timestamp":1711482021000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10318181\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":66,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3333290","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,4]]}}}