{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:45:49Z","timestamp":1776955549602,"version":"3.51.4"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"DARPA","doi-asserted-by":"publisher","award":["HR0011-18-2-0032"],"award-info":[{"award-number":["HR0011-18-2-0032"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF-1564302"],"award-info":[{"award-number":["CCF-1564302"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF-2112665"],"award-info":[{"award-number":["CCF-2112665"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100005144","name":"Qualcomm","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005144","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004358","name":"Samsung Electronics","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]},{"name":"C-DEN Center"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1109\/tcad.2023.3334591","type":"journal-article","created":{"date-parts":[[2023,11,20]],"date-time":"2023-11-20T19:21:38Z","timestamp":1700508098000},"page":"1218-1231","source":"Crossref","is-referenced-by-count":29,"title":["PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement"],"prefix":"10.1109","volume":"43","author":[{"given":"Suhyeong","family":"Choi","sequence":"first","affiliation":[{"name":"Semiconductor R&D Center, Samsung Electronics, Hwaseong, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9384-5277","authenticated-orcid":false,"given":"Jinwook","family":"Jung","sequence":"additional","affiliation":[{"name":"Physical Design Department, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4490-5018","authenticated-orcid":false,"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6488-4349","authenticated-orcid":false,"given":"Minsoo","family":"Kim","sequence":"additional","affiliation":[{"name":"Advanced Technology Group, NVIDIA Corporation, Austin, TX, USA"}]},{"given":"Chul-Hong","family":"Park","sequence":"additional","affiliation":[{"name":"Semiconductor Business, Hyundai MOBIS, Seoul, South Korea"}]},{"given":"Bodhisatta","family":"Pramanik","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA"}]},{"given":"Dooseok","family":"Yoon","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717782"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1117\/12.2514942"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP52707.2021.00009"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3093015"},{"key":"ref5","first-page":"1","article-title":"A novel framework for DTCO: Fast and automatic routability assessment with machine learning for sub-3nm technology options","volume-title":"Proc. IEEE Symp. VLSI Technol.","author":"Chidambaram"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2954301"},{"key":"ref8","article-title":"Near-optimal bin packing algorithms","author":"Johnson","year":"1973"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3041665"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2750072"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3229442"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3209530"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1117\/12.2554025"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3038255"},{"key":"ref16","first-page":"2579","article-title":"Visualizing data using t-SNE","volume":"9","author":"Maaten","year":"2008","journal-title":"J. Mach. Learn. Res."},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993617"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/EDTM.2019.8731234"},{"key":"ref19","article-title":"FreePDK3: A novel PDK for physical verification at the 3nm node","author":"Sadangi","year":"2021"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IITC51362.2021.9537541"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573515"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012595"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3186657"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323975"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.728919"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNSE.2022.3217185"},{"key":"ref27","volume-title":"68-95-99.7 rule","year":"2023"},{"key":"ref28","volume-title":"Applied materials logic master class","year":"2023"},{"key":"ref29","volume-title":"Artificial netlist generator","year":"2023"},{"key":"ref30","volume-title":"Backside power delivery and bold bets at Intel","author":"O\u2019Laughlin","year":"2022"},{"key":"ref31","volume-title":"Cadence QRC extraction user guide","year":"2023"},{"key":"ref32","volume-title":"Cadence voltus user guide","year":"2023"},{"key":"ref33","volume-title":"FreePDK3 predictive process design kit","year":"2023"},{"key":"ref34","volume-title":"GDT to GDS format translator","year":"2023"},{"key":"ref35","volume-title":"H2O AutoML","year":"2023"},{"key":"ref36","volume-title":"IEEE international roadmap for devices and systems (IRDS)","year":"2020"},{"key":"ref37","volume-title":"OpenCores: Open source IP-cores","year":"2023"},{"key":"ref38","volume-title":"OpenDB","year":"2023"},{"key":"ref39","volume-title":"Siemens EDA calibre user guide","year":"2023"},{"key":"ref40","volume-title":"Synopsys design compiler user guide","year":"2023"},{"key":"ref41","volume-title":"Synopsys IC compiler II user guide","year":"2023"},{"key":"ref42","volume-title":"Synopsys StarRC user guide","year":"2023"},{"key":"ref43","volume-title":"Synopsys DTCO flow: Technology development","year":"2023"},{"key":"ref44","volume-title":"The PROBE3.0 framework","year":"2023"},{"key":"ref45","volume-title":"Z3 SMT solver"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/43\/10477239\/10322780-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10477239\/10322780.pdf?arnumber=10322780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T20:29:38Z","timestamp":1711484978000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10322780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":45,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3334591","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,4]]}}}