{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T21:45:22Z","timestamp":1755035122181,"version":"3.37.3"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274100","U23A20351","61871242"],"award-info":[{"award-number":["62274100","U23A20351","61871242"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Key Research and Development Program of Ningbo City","award":["2023Z071"],"award-info":[{"award-number":["2023Z071"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1109\/tcad.2023.3337279","type":"journal-article","created":{"date-parts":[[2023,11,28]],"date-time":"2023-11-28T19:16:52Z","timestamp":1701199012000},"page":"1093-1106","source":"Crossref","is-referenced-by-count":3,"title":["Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting"],"prefix":"10.1109","volume":"43","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0874-4518","authenticated-orcid":false,"given":"Hongyang","family":"Pan","sequence":"first","affiliation":[{"name":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3831-3876","authenticated-orcid":false,"given":"Yinshui","family":"Xia","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lunyao","family":"Wang","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5718-4822","authenticated-orcid":false,"given":"Zhufei","family":"Chu","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1995.250098"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3154-8"},{"volume-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"Micheli","key":"ref3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-374364-0.50013-8"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429513"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858312"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-24605-3_37"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116379"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287671"},{"key":"ref10","first-page":"1","article-title":"Scalable generic logic synthesis: One approach to rule them all","volume-title":"Proc. 56th Annu. Design Autom. Conf.","author":"Riener"},{"key":"ref11","first-page":"1","article-title":"Exact synthesis for logic synthesis applications with complex constraints","volume-title":"Proc. 26th Int. Workshop Logic Synth. (IWLS)","author":"Testa"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/s41534-021-00514-y"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2925392"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643505"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30201-8_48"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137287"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-022-1981-4"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/10722167_15"},{"article-title":"SAT-based exact synthesis for multi-level logic networks","year":"2019","author":"Haaswijk","key":"ref21"},{"volume-title":"Also: Advanced logic synthesis and optimization tool","year":"2023","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.2307\/2308219"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"article-title":"Exact circuit synthesis","volume-title":"Proc. Int. Workshop Logic Synth.","author":"Drechsler","key":"ref25"},{"key":"ref26","article-title":"Practical SAT\u2014A tutorial on applied satisfiability solving","author":"E\u00e9n","year":"2007","journal-title":"Slides Invited Talk FMCAD"},{"key":"ref27","volume-title":"The Art of Computer Programming","volume":"4A","author":"Knuth","year":"2011"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664059"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927103"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342027"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2897703"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465888"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.artint.2021.103572"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CompComm.2018.8780746"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1080\/0952813X.2019.1672798"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1142\/8323"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/S0377-0427(00)00393-9"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/s11424-007-9027-0"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCA.2005.1528094"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0227"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/264995.264996"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2017.44"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117208"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"ref45","first-page":"1","article-title":"LUT mapping and optimization for majority-inverter graphs","volume-title":"Proc. 25th Int. Workshop Logic Synth. (IWLS)","author":"Haaswijk"},{"volume-title":"Percy: A header-only exact synthesis library","year":"2019","key":"ref46"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715185"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref49","article-title":"An automated testing and debugging toolkit for gate-level logic synthesis applications","author":"Lee","year":"2022","journal-title":"arXiv:2207.13487"},{"volume-title":"ABC: System for sequential logic synthesis and formal verification","year":"2022","key":"ref50"},{"volume-title":"Mockturtle: A head-only library for logic synthesis and logic optimization","year":"2023","key":"ref51"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718374"},{"article-title":"An approach to disjoint-support decomposition of logic functions","year":"2001","author":"Mishchenko","key":"ref53"},{"volume-title":"EPFL combinational benchmark suite","year":"2023","key":"ref54"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/10477239\/10330666.pdf?arnumber=10330666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T20:28:38Z","timestamp":1711484918000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10330666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":54,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2023.3337279","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2024,4]]}}}