{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:13:29Z","timestamp":1781194409731,"version":"3.54.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2021ZD0114702"],"award-info":[{"award-number":["2021ZD0114702"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62374138"],"award-info":[{"award-number":["62374138"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100013314","name":"Higher Education Discipline Innovation Project","doi-asserted-by":"publisher","award":["B18001"],"award-info":[{"award-number":["B18001"]}],"id":[{"id":"10.13039\/501100013314","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,3]]},"DOI":"10.1109\/tcad.2024.3447218","type":"journal-article","created":{"date-parts":[[2024,8,21]],"date-time":"2024-08-21T19:29:23Z","timestamp":1724268563000},"page":"1003-1016","source":"Crossref","is-referenced-by-count":5,"title":["A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections"],"prefix":"10.1109","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-7958-8485","authenticated-orcid":false,"given":"Xun","family":"Jiang","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7054-384X","authenticated-orcid":false,"given":"Jiarui","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Computer Science and the School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3787-1534","authenticated-orcid":false,"given":"Jing","family":"Mai","sequence":"additional","affiliation":[{"name":"School of Computer Science and the School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7323-5052","authenticated-orcid":false,"given":"Zhixiong","family":"Di","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Science and Engineering, Southwest Jiaotong University, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits and the Beijing Advanced Innovation Center for Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045175"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"ref5","first-page":"215","article-title":"Detailed routing algorithm for allocating wire segments in field-programmable gate arrays","volume-title":"Proc. Phys. Design Workshop","author":"Lemieux"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502356"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2768416"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00017"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3491236"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323897"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00093"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00095"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174246"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3406959"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3031259"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON58565.2023.10396248"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3340554"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/iseda62518.2024.10617535"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3313101"},{"key":"ref20","volume-title":"Vivado","year":"2024"},{"key":"ref21","volume-title":"Quartus","year":"2024"},{"key":"ref22","volume-title":"Xilinx ultrascale architecture","year":"2024"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549434"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3117505"},{"key":"ref26","volume-title":"Gurobi Optimizer Reference Manual","year":"2022"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3104255"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3053191"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2886419"},{"key":"ref30","volume-title":"UltraScale Architecture Clocking Resources User Guide (UG572)","year":"2023"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3567898"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/10896910\/10643154.pdf?arnumber=10643154","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T18:43:09Z","timestamp":1763750589000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10643154\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3]]},"references-count":31,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2024.3447218","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3]]}}}