{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T02:02:02Z","timestamp":1769824922566,"version":"3.49.0"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Key Research and Development Program of China","award":["2020YFA0711900"],"award-info":[{"award-number":["2020YFA0711900"]}]},{"name":"National Key Research and Development Program of China","award":["2020YFA0711901"],"award-info":[{"award-number":["2020YFA0711901"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China Research Projects","doi-asserted-by":"publisher","award":["62141407"],"award-info":[{"award-number":["62141407"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China Research Projects","doi-asserted-by":"publisher","award":["62304052"],"award-info":[{"award-number":["62304052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China Research Projects","doi-asserted-by":"publisher","award":["62474050"],"award-info":[{"award-number":["62474050"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China Research Projects","doi-asserted-by":"publisher","award":["62474051"],"award-info":[{"award-number":["62474051"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China Research Projects","doi-asserted-by":"publisher","award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,3]]},"DOI":"10.1109\/tcad.2024.3455932","type":"journal-article","created":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T17:58:15Z","timestamp":1725645495000},"page":"818-831","source":"Crossref","is-referenced-by-count":3,"title":["VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis"],"prefix":"10.1109","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3512-0320","authenticated-orcid":false,"given":"Aidong","family":"Zhao","sequence":"first","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-5071-0674","authenticated-orcid":false,"given":"Ruiyu","family":"Lyu","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8977-2725","authenticated-orcid":false,"given":"Xuyang","family":"Zhao","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7315-3150","authenticated-orcid":false,"given":"Zhaori","family":"Bi","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2164-8175","authenticated-orcid":false,"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8936-3945","authenticated-orcid":false,"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2648-5232","authenticated-orcid":false,"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"given":"Yangfeng","family":"Su","sequence":"additional","affiliation":[{"name":"School of Mathematical Sciences, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8097-4053","authenticated-orcid":false,"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"Microelectronics Department, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]}],"member":"263","reference":[{"key":"ref1","first-page":"147","article-title":"Ensemble methods for convex regression with applications to geometric programming based circuit design","volume-title":"Proc. 29th Int. Conf. Mach. Learn.","author":"Hannah"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.905671"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SOCPAR.2010.5686736"},{"key":"ref4","first-page":"61","article-title":"Improved support vector machine regression for analog circuits macromodeling using efficient kernel functions","volume-title":"Proc. IEEE Int. Workshop Symbol. Numer. Methods, Model. Appl. Circuit Design","author":"Boolchandani"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729461"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-009-9361-3"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.04.003"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref9","first-page":"3306","article-title":"Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design","volume-title":"Proc. 35th Int. Conf. Int. Conf. Mach. Learn.","author":"Lyu"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3453474"},{"key":"ref11","first-page":"2187","article-title":"Parallel Bayesian optimization of multiple noisy objectives with expected hypervolume improvement","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Daulton"},{"key":"ref12","volume-title":"Max-Value Entropy Search for Multi-Objective Bayesian Optimization","author":"Belakaria","year":"2019"},{"key":"ref13","first-page":"295","article-title":"High dimensional Bayesian optimisation and bandits via additive models","volume-title":"Proc. 32nd Int. Conf. Mach. Learn.","author":"Kandasamy"},{"key":"ref14","first-page":"745","article-title":"Batched large-scale Bayesian optimization in high-dimensional spaces","volume-title":"Proc. Int. Conf. Artif. Intell. Statist. (AISTATS)","author":"Wang"},{"key":"ref15","first-page":"4752","article-title":"A framework for Bayesian optimization in embedded subspaces","volume-title":"Proc. 36th Int. Conf. Int. Conf. Mach. Learn.","author":"Nayebi"},{"key":"ref16","first-page":"28488","article-title":"Monte Carlo tree search based variable selection for high dimensional Bayesian optimization","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Song"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3147431"},{"key":"ref18","first-page":"5496","article-title":"Scalable global optimization via local Bayesian optimization","volume-title":"Proc. 33th Int. Conf. Neural Inf. Process. Syst.","author":"Eriksson"},{"issue":"3","key":"ref19","first-page":"1","article-title":"D3PBO: Dynamic domain decomposition-based parallel Bayesian optimization for large-scale analog circuit sizing","volume":"29","author":"Zhao","year":"2024","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"ref20","first-page":"19511","article-title":"Learning search space partition for black-box optimization using Monte Carlo tree search","volume-title":"Proc. 34th Int. Conf. Neural Inf. Process. Syst.","author":"Wang"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247994"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2005.851274"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3121263"},{"key":"ref24","first-page":"507","article-title":"Multi-objective Bayesian optimization over high-dimensional search spaces","volume-title":"Proc. 38th Conf. Uncertain. Artif. Intell.","author":"Daulton"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2013.2281535"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1016\/j.cor.2016.06.021"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.7551\/mitpress\/3206.001.0001"},{"key":"ref29","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-77974-2","volume-title":"Computational Geometry Algorithms and Applications","author":"Berg","year":"2008"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2007.894202"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/11871842_29"},{"key":"ref32","volume-title":"Reinforcement Learning: An Introduction","author":"Sutton","year":"2018"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/BF01890115"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.ejor.2006.08.008"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2019.2909636"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1162\/106365603321828970"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1137\/S1052623496306450"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/BioCAS.2011.6107808"},{"key":"ref39","first-page":"563","article-title":"A 12-bit 50-MS\/s pipelined analog-to-digital converter in 65 nm CMOS","volume-title":"Proc. 10th IEEE Int. Conf. Solid-State Integr. Circuit Technol.","author":"Shu"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-010-9453-0"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/10896910\/10667666.pdf?arnumber=10667666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T12:04:51Z","timestamp":1740139491000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10667666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3]]},"references-count":40,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2024.3455932","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3]]}}}