{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:40:08Z","timestamp":1747806008955,"version":"3.41.0"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62372227"],"award-info":[{"award-number":["62372227"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tcad.2024.3509798","type":"journal-article","created":{"date-parts":[[2024,11,29]],"date-time":"2024-11-29T18:52:54Z","timestamp":1732906374000},"page":"2424-2437","source":"Crossref","is-referenced-by-count":0,"title":["Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection"],"prefix":"10.1109","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1111-7859","authenticated-orcid":false,"given":"Longlong","family":"Lu","sequence":"first","affiliation":[{"name":"State Key Laboratory for Novel Software Technology and the Software Institute, Nanjing University, Nanjing, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4011-5350","authenticated-orcid":false,"given":"Minxue","family":"Pan","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Novel Software Technology and the Software Institute, Nanjing University, Nanjing, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yifei","family":"Lu","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Novel Software Technology and the Software Institute, Nanjing University, Nanjing, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuandong","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory for Novel Software Technology and the School of Computer Science, Nanjing University, Nanjing, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511674730"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878304"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/WCADM.1995.514642"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/b135575"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SIGTELCOM.2017.7849815"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359585"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-54862-8_13"},{"volume-title":"The Designer\u2019s Guide to VHDL","year":"2010","author":"Ashenden","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2813885.2737967"},{"issue":"1","key":"ref10","doi-asserted-by":"crossref","first-page":"133","DOI":"10.1016\/S0167-9317(00)80065-9","article-title":"Asynchronous circuits and systems: A promising design alternative","volume":"54","author":"Renaudin","year":"2000","journal-title":"Microelectron. Eng."},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3233\/978-1-60750-774-1-287"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2012.22"},{"key":"ref13","volume":"5","author":"Barbe","year":"2013","journal-title":"Very Large Scale Integration (VLSI): Fundamentals and Applications"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-012-0244-z"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00021"},{"key":"ref16","first-page":"1","volume-title":"Model Checking and the State Explosion Problem","author":"Clarke","year":"2012"},{"key":"ref17","first-page":"305","volume-title":"Satisfiability Modulo Theories","author":"Barrett","year":"2018"},{"volume-title":"The Theory and Practice of Concurrency","year":"1998","author":"Roscoe","key":"ref18"},{"volume-title":"A Structural Approach to Operational Semantics","year":"1981","author":"Plotkin","key":"ref19"},{"key":"ref20","first-page":"1","article-title":"Modeling with systemverilog in a synopsys synthesis design flow using Leda, VCS, design compiler and formality","volume-title":"Proc. SNUG Europe","author":"Sutherland"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3622805"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/322374.322380"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2017.8292066"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.21236\/ADA605735"},{"volume-title":"The Go Programming Language","year":"2015","author":"Donovan","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.entcs.2005.04.014"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/45.1.12"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC58294.2023.10239640"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2008.18"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2013.21"},{"key":"ref31","first-page":"3","article-title":"Click elements: An implementation style for data-driven compilation","volume-title":"Proc. IEEE Symp. Asynchronous Circuits Syst.","author":"Peeters"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3437992.3439916"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-89439-1_25"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2892208.2892232"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2676726.2676964"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3009837.3009847"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2873052"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/360248.360252"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3180155.3180157"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(82)90125-6"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/73560.73562"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11007940\/10771970.pdf?arnumber=10771970","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:03:28Z","timestamp":1747803808000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10771970\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":41,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2024.3509798","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}