{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T18:50:28Z","timestamp":1763751028126,"version":"3.45.0"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61771338"],"award-info":[{"award-number":["61771338"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1109\/tcad.2024.3520024","type":"journal-article","created":{"date-parts":[[2024,12,18]],"date-time":"2024-12-18T14:34:54Z","timestamp":1734532494000},"page":"2827-2831","source":"Crossref","is-referenced-by-count":1,"title":["SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration"],"prefix":"10.1109","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-5966-1388","authenticated-orcid":false,"given":"Ning","family":"Li","sequence":"first","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dejian","family":"Li","sequence":"additional","affiliation":[{"name":"Beijing Smartchip Microelectronics Technology Company Ltd., Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5846-3970","authenticated-orcid":false,"given":"Zhipeng","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2648-7358","authenticated-orcid":false,"given":"Peiguang","family":"Jing","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8648-2092","authenticated-orcid":false,"given":"Sio","family":"Hang Pun","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, The University of Macau, Macau, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5949-6587","authenticated-orcid":false,"given":"Yu","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.cosrev.2020.100303"},{"key":"ref2","article-title":"Language models are few-shot learners","author":"Brown","year":"2020","journal-title":"arXiv:2005.14165"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TITS.2022.3195555"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116477"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062262"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2728814"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2629610"},{"volume-title":"A coarse grain reconfigurable array (CGRA) for statically scheduled data flow computing","year":"2017","author":"Nicol","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3357375"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589081"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3253686"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2023.3268126"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3344536"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527426"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3132551"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995277"},{"key":"ref18","first-page":"1","article-title":"Morpher: An open-source integrated compilation and simulation framework for CGRA","volume-title":"Proc. 5th Workshop Open-Source EDA Technol. (WOSET)","author":"Wijerathne"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11044910\/10806802.pdf?arnumber=10806802","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T18:43:12Z","timestamp":1763750592000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10806802\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7]]},"references-count":18,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2024.3520024","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2025,7]]}}}