{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:29:45Z","timestamp":1781195385665,"version":"3.54.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61925203"],"award-info":[{"award-number":["61925203"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U22B2021"],"award-info":[{"award-number":["U22B2021"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Major Key Project of PCL","award":["PCL2023A03"],"award-info":[{"award-number":["PCL2023A03"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1109\/tcad.2024.3524463","type":"journal-article","created":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T14:33:46Z","timestamp":1735655626000},"page":"2585-2598","source":"Crossref","is-referenced-by-count":4,"title":["A Delay-Driven Iterative Technology Mapping Framework"],"prefix":"10.1109","volume":"44","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-8205-4564","authenticated-orcid":false,"given":"Junfeng","family":"Liu","sequence":"first","affiliation":[{"name":"School of Computer Science and Engineering, Beihang University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-7525-9375","authenticated-orcid":false,"given":"Liwei","family":"Ni","sequence":"additional","affiliation":[{"name":"Department of Optoelectronic Information and Fiber Optic Communication, Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1054-5501","authenticated-orcid":false,"given":"Lei","family":"Chen","sequence":"additional","affiliation":[{"name":"Noah’s Ark Lab, Huawei Technologies, Hong Kong, SAR, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1669-5954","authenticated-orcid":false,"given":"Xing","family":"Li","sequence":"additional","affiliation":[{"name":"Noah’s Ark Lab, Huawei Technologies, Hong Kong, SAR, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5016-0390","authenticated-orcid":false,"given":"Qinghua","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Artificial Intelligence and Big Data, Hefei University, Hefei, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7145-9391","authenticated-orcid":false,"given":"Xingquan","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Optoelectronic Information and Fiber Optic Communication, Pengcheng Laboratory, Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4050-0443","authenticated-orcid":false,"given":"Shuai","family":"Ma","sequence":"additional","affiliation":[{"name":"School of Computer Science and Engineering, Beihang University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247905"},{"key":"ref2","volume-title":"On Algorithms for Technology Mapping","author":"Chatterjee","year":"2007"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473932"},{"key":"ref4","article-title":"A circuit domain generalization framework for efficient logic synthesis in chip design","author":"Wang","year":"2023","journal-title":"arXiv:2309.03208"},{"key":"ref5","first-page":"1","article-title":"Mapping and retiming revisited","volume-title":"Proc. Int. Workshop Logic Synth. (IWLS)","author":"Mishchenko"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00059"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3379016"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586230"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref11","first-page":"475","article-title":"A novel technology mapper for complex universal gates","volume-title":"Proc. Asia South Pacific Design Autom. Conf. (ASPDAC)","author":"Wu"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751913"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219085"},{"key":"ref14","first-page":"209","article-title":"On the complexity of minimum-delay gate resizing\/technology mapping under load-dependent delay model","volume-title":"Proc. Int. Workshop Logic Synth. (IWLS)","author":"Murgai"},{"key":"ref15","article-title":"Technology mapping with Boolean matching, supergates and choices","author":"Mishchenko"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2484299"},{"key":"ref17","volume-title":"Logic Synthesis for VLSI Design","author":"Rudell","year":"1989"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323999"},{"key":"ref19","article-title":"SIS: A system for sequential circuit synthesis","author":"Sentovich","year":"1992"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(99)00023-1"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927194"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907067"},{"key":"ref23","volume-title":"Logical Effort: Designing Fast CMOS Circuits","author":"Sutherland","year":"1999"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.811455"},{"key":"ref25","first-page":"1","article-title":"The EPFL combinational benchmark suite","volume-title":"Proc. Int. Workshop Logic Synthesis (IWLS)","author":"Amar\u00fa"},{"key":"ref26","article-title":"A review of Bayesian methods in electronic design automation","author":"Gao","year":"2023","journal-title":"arXiv:2304.09723"},{"key":"ref27","first-page":"14650","article-title":"Black-box optimization with local generative surrogates","volume-title":"Proc. Annu. Conf. Neural Inf. Process. Syst. (NeurIPS)","volume":"33","author":"Shirobokov"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3167858"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774632"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323856"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323703"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1613\/jair.1.13643"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473983"},{"key":"ref34","first-page":"1","article-title":"IWLS 2005 benchmarks","volume-title":"Proc. Int. Workshop Logic Synthesis (IWLS)","volume":"9","author":"Albrecht"},{"key":"ref35","article-title":"OpenABC-D: A large-scale dataset for machine learning guided integrated circuit synthesis","author":"Chowdhury","year":"2021","journal-title":"arXiv:2110.11292"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref37","volume-title":"SkyWater-PDK.","year":"2021"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530460"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11044910\/10818751.pdf?arnumber=10818751","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T18:43:14Z","timestamp":1763750594000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10818751\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7]]},"references-count":38,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2024.3524463","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,7]]}}}