{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:13:42Z","timestamp":1759331622414,"version":"build-2065373602"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T00:00:00Z","timestamp":1759276800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T00:00:00Z","timestamp":1759276800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T00:00:00Z","timestamp":1759276800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Key Research and Development Program Young Scientist Project of China","award":["NO.2023YFB4402500"],"award-info":[{"award-number":["NO.2023YFB4402500"]}]},{"name":"Pre research on shared information system equipment","award":["No.31513010401"],"award-info":[{"award-number":["No.31513010401"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025,10]]},"DOI":"10.1109\/tcad.2025.3555507","type":"journal-article","created":{"date-parts":[[2025,3,28]],"date-time":"2025-03-28T23:35:17Z","timestamp":1743204917000},"page":"3724-3737","source":"Crossref","is-referenced-by-count":0,"title":["POFGSP: Priority-Based Out-of-Order Scheduling and Fine-Grain Status Polling for SSD Performance Improvement"],"prefix":"10.1109","volume":"44","author":[{"given":"Wentian","family":"Wu","sequence":"first","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7452-3360","authenticated-orcid":false,"given":"Qianhui","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5300-8255","authenticated-orcid":false,"given":"Tong","family":"Qu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-2259-6063","authenticated-orcid":false,"given":"Qi","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9845-5649","authenticated-orcid":false,"given":"Zongliang","family":"Huo","sequence":"additional","affiliation":[{"name":"Advanced Memory Research Center, Yangtze Memory Technologies Company Ltd., Wuhan, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2384-9037","authenticated-orcid":false,"given":"Tianchun","family":"Ye","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2677425"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757454"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454296"},{"volume-title":"InfiniBand Roadmap","year":"2024","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC50251.2020.00013"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3288748"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el.2019.3526"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2588491"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835961"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237035"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00023"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3563456"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3676884"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.209"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-016-0449-y"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2010.5496715"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542324"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555790"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995912"},{"volume-title":"Open NAND flash interface specifications","year":"2024","key":"ref20"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2019.00025"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3385073"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310322"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2824818"},{"key":"ref25","first-page":"49","article-title":"MQSim: A framework for enabling realistic studies of modern multi-queue SSD devices","volume-title":"Proc. USENIX Conf. File Storage Technol. (FAST)","author":"Tavakkol"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3232997"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2024.3407367"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3385290"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3266363"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3332829"},{"journal-title":"Gen 3 TLC 3D NAND Flash Memory X2-9060","article-title":"Yangtze Memory Technol. Co","year":"2019","key":"ref31"},{"journal-title":"Gen 2 TLC 3D NAND Flash Memory X1-9050","article-title":"Yangtze Memory Technol. C","year":"2019","key":"ref32"},{"volume-title":"3D NAND flash memory PART MT29F1T08EBLCHD4-R:C","year":"2024","key":"ref33"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636097"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2017.8277544"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185391"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11155107\/10943242.pdf?arnumber=10943242","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T13:49:36Z","timestamp":1759240176000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10943242\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10]]},"references-count":36,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3555507","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2025,10]]}}}