{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T18:19:00Z","timestamp":1769019540505,"version":"3.49.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2020YFA0711900"],"award-info":[{"award-number":["2020YFA0711900"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2020YFA0711901"],"award-info":[{"award-number":["2020YFA0711901"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92473206"],"award-info":[{"award-number":["92473206"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62474050"],"award-info":[{"award-number":["62474050"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62304052"],"award-info":[{"award-number":["62304052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92473207"],"award-info":[{"award-number":["92473207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62474051"],"award-info":[{"award-number":["62474051"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62090025"],"award-info":[{"award-number":["62090025"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1109\/tcad.2025.3573228","type":"journal-article","created":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T13:04:51Z","timestamp":1748005491000},"page":"31-44","source":"Crossref","is-referenced-by-count":7,"title":["Atelier: An Automated Analog Circuit Design Framework via Multiple Large Language Model-Based Agents"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-2362-0361","authenticated-orcid":false,"given":"Jinyi","family":"Shen","sequence":"first","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-5372-3525","authenticated-orcid":false,"given":"Zihao","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"given":"Ji","family":"Zhuang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9111-8474","authenticated-orcid":false,"given":"Jiangli","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Computer Science, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2164-8175","authenticated-orcid":false,"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9216-1921","authenticated-orcid":false,"given":"Li","family":"Shang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7315-3150","authenticated-orcid":false,"given":"Zhaori","family":"Bi","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8936-3945","authenticated-orcid":false,"given":"Changhao","family":"Yan","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2648-5232","authenticated-orcid":false,"given":"Dian","family":"Zhou","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8097-4053","authenticated-orcid":false,"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2768826"},{"key":"ref2","first-page":"3306","article-title":"Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Lyu"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3054811"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218757"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586139"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3435692"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.46777"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.945301"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3295737"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546840"},{"key":"ref12","first-page":"44","article-title":"Topology synthesis of analog circuits based on adaptively generated building blocks","volume-title":"Proc. 45th Annu. Design Autom. Conf.","author":"Das"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2010.2093581"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.engappai.2019.01.012"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586306"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774676"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3296374"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3153437"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED57927.2023.10129336"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3245979"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430634"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137086"},{"key":"ref23","article-title":"VerilogEval: Evaluating large language models for Verilog code generation","author":"Liu","year":"2023","journal-title":"arXiv:2309.07544"},{"key":"ref24","volume-title":"LADAC: Large language model-driven auto-designer for analog circuits","author":"Liu","year":"2024"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676816"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v39i1.32016"},{"key":"ref27","article-title":"LaMAGIC: Language-model-based topology generation for analog integrated circuits","author":"Chang","year":"2024","journal-title":"arXiv:2407.18269"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3655903"},{"key":"ref29","volume-title":"Llama 3 model card","year":"2024"},{"key":"ref30","article-title":"GPT-4 technical report","volume-title":"OpenAI","year":"2023"},{"key":"ref31","article-title":"ChatGLM: A family of large language models from GLM-130B to GLM-4 all tools","author":"GLM","year":"2024","journal-title":"arXiv:2406.12793"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-47101-3"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"key":"ref34","article-title":"Llama: Open and efficient foundation language models","author":"Touvron","year":"2023","journal-title":"arXiv:2302.13971"},{"key":"ref35","volume-title":"Llama 2: Open foundation and fine-tuned chat models","author":"Touvron","year":"2023"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.patter.2025.101260"},{"key":"ref37","volume-title":"Chain-of-thought prompting elicits reasoning in large language models","author":"Wei","year":"2023"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v38i16.29720"},{"key":"ref39","first-page":"9459","article-title":"Retrieval-augmented generation for knowledge-intensive NLP tasks","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","volume":"33","author":"Lewis"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/81.948432"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8111268"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-32494-1_4"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3040718.3040732"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-24694-7_73"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/4.748185"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11329484\/11012698.pdf?arnumber=11012698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T22:01:14Z","timestamp":1768255274000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11012698\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":45,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3573228","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,1]]}}}