{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T06:09:29Z","timestamp":1767766169036,"version":"3.48.0"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"ASE Group ChungLi and NSTC of Taiwan","award":["MOST-110-2221-E-011-152-MY2"],"award-info":[{"award-number":["MOST-110-2221-E-011-152-MY2"]}]},{"name":"ASE Group ChungLi and NSTC of Taiwan","award":["NSTC 113-2221-E-011-088"],"award-info":[{"award-number":["NSTC 113-2221-E-011-088"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1109\/tcad.2025.3578328","type":"journal-article","created":{"date-parts":[[2025,6,10]],"date-time":"2025-06-10T13:52:08Z","timestamp":1749563528000},"page":"552-556","source":"Crossref","is-referenced-by-count":0,"title":["Optimization Heuristics for Grid-Based Integer Linear Programming Package Substrate Router"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-6552-201X","authenticated-orcid":false,"given":"Chen-Yu","family":"Hsieh","sequence":"first","affiliation":[{"name":"Department of Computer Science and Information Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-5864-1585","authenticated-orcid":false,"given":"Yu-En","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Information Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6703-004X","authenticated-orcid":false,"given":"Yi-Yu","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Information Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"519","article-title":"Routability-driven bump assignment for chip-package co-design","volume-title":"Proc. ASP-DAC","author":"Hsu"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116421"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431568"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009151"},{"volume-title":"Design guidelines for cypress ball grid array (BGA) packaged devices","year":"2019","key":"ref5"},{"key":"ref6","first-page":"581","article-title":"Single-layer fanout routing and routability analysis for ball grid","volume-title":"Proc. ICCAD","author":"Yu"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055146"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870064"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E92.A.2998"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E92.A.1433"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3579843"},{"volume-title":"Gurobi optimizer 8.1","year":"2020","key":"ref12"},{"volume-title":"Cadence allegro package designer 16.6","year":"2020","key":"ref13"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11329484\/11029488.pdf?arnumber=11029488","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T05:58:17Z","timestamp":1767765497000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11029488\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3578328","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2026,1]]}}}