{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T16:02:33Z","timestamp":1780675353097,"version":"3.54.1"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"JC STEM Laboratory of Intelligent Design Automation"},{"name":"Hong Kong Jockey Club Charities Trust"},{"DOI":"10.13039\/501100004787","name":"Research Grants Council of Hong Kong, SAR","doi-asserted-by":"publisher","award":["CUHK14211324"],"award-info":[{"award-number":["CUHK14211324"]}],"id":[{"id":"10.13039\/501100004787","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004787","name":"Research Grants Council of Hong Kong, SAR","doi-asserted-by":"publisher","award":["CUHK14211824"],"award-info":[{"award-number":["CUHK14211824"]}],"id":[{"id":"10.13039\/501100004787","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100014103","name":"Science and Technology Innovation Key Research and Development Program of Chongqing","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100014103","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1109\/tcad.2025.3580511","type":"journal-article","created":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T13:40:39Z","timestamp":1750167639000},"page":"428-440","source":"Crossref","is-referenced-by-count":1,"title":["HiePlace: Efficient Hierarchical PCB Placement"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-0971-070X","authenticated-orcid":false,"given":"Shanyi","family":"Li","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, SAR, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2972-8770","authenticated-orcid":false,"given":"Zhen","family":"Zhuang","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, SAR, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mingyu","family":"Liu","sequence":"additional","affiliation":[{"name":"Industrial Software Platform Cloud Service Product Department, Huawei Cloud Computing Technology Company Ltd., Shenzhen, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Weihua","family":"Sheng","sequence":"additional","affiliation":[{"name":"Design Automation Lab, Huawei HiSilicon, Huawei, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, SAR, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7348-5625","authenticated-orcid":false,"given":"Tsung-Yi","family":"Ho","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, SAR, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317803"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2925989"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247681"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633321"},{"key":"ref5","first-page":"170","article-title":"A unified printed circuit board routing algorithm with complicated constraints and differential pairs","volume-title":"Proc. IEEE\/ACM Asia South Pacific Design Autom. Conf. (ASPDAC)","author":"Lin"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3059100"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240772"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2114531"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320084"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428007"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICASIC.2001.982523"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2011.8"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1214\/ss\/1177011077"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3047724"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3002570"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s10845-010-0444-x"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084652"},{"key":"ref19","first-page":"24019","article-title":"MaskPlace: Fast chip placement via reinforced visual representation learning","volume-title":"Proc. Annu. Conf. Neural Inf. Process. Syst. (NeurIPS)","author":"Lai"},{"key":"ref20","first-page":"26350","article-title":"The policy-gradient placement and generative routing neural networks for chip design","volume-title":"Proc. Annu. Conf. Neural Inf. Process. Syst. (NeurIPS)","author":"Cheng"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3505170.3511478"},{"key":"ref22","first-page":"16508","article-title":"On joint learning for solving placement and routing in chip design","volume-title":"Proc. Annu. Conf. Neural Inf. Process. Syst. (NeurIPS)","author":"Cheng"},{"key":"ref23","first-page":"18346","article-title":"ChiPFormer: Transferable chip placement via offline decision transformer","volume-title":"Proc. Int. Conf. Mach. Learn. (ICML)","author":"Lai"},{"key":"ref24","first-page":"1","article-title":"Multi-package co-design for chiplet integration","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput.-Aided Design (ICCAD)","author":"Zhuang"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3347302"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347979"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.876374"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483939"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870076"},{"key":"ref30","volume-title":"Gurobi optimizer","year":"2024"},{"key":"ref31","volume-title":"ASPDAC-submission-PCB-layout\/PCBBenchmarks","year":"2020"},{"key":"ref32","volume-title":"Quilter 2025","year":"2025"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11329484\/11039086.pdf?arnumber=11039086","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T22:01:11Z","timestamp":1768255271000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11039086\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":32,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3580511","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,1]]}}}