{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T15:57:27Z","timestamp":1769183847029,"version":"3.49.0"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"name":"Research Grants Council of the Hong Kong Special Administrative Region, China","award":["14218422"],"award-info":[{"award-number":["14218422"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,2]]},"DOI":"10.1109\/tcad.2025.3587534","type":"journal-article","created":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T23:19:10Z","timestamp":1752103150000},"page":"659-672","source":"Crossref","is-referenced-by-count":0,"title":["An Open-Source High-Concurrency and High-Performance Parallel Router for UltraScale FPGAs"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-3189-7868","authenticated-orcid":false,"given":"Wenhao","family":"Lin","sequence":"first","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-7889-4481","authenticated-orcid":false,"given":"Xinshi","family":"Zang","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-0060-650X","authenticated-orcid":false,"given":"Zewen","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0623-1590","authenticated-orcid":false,"given":"Evangeline F. Y.","family":"Young","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Hong Kong"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3491236"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056782"},{"key":"ref4","first-page":"111","article-title":"Pathfinder: A negotiation-based performance-driven router for FPGAs","volume-title":"Proc. 3rd Int. ACM Symp. Field-Program. Gate Arrays","author":"McMurchie"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045175"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00017"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3188964"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2901243"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174246"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3649476.3658714"},{"key":"ref11","volume-title":"Runtime-first FPGA interchange routing contest @ FPGA\u201924","author":"Hung","year":"2024"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL64840.2024.00017"},{"key":"ref13","first-page":"21","article-title":"Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput.-Aided Design","author":"Li"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2013.08.001"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00030"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL53798.2021.00046"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577299"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3184281"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021732"},{"key":"ref20","first-page":"1","article-title":"AceRoute: Adaptive compute-efficient FPGA routing with pluggable intra-connection bidirectional exploration","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput.-Aided Design (ICCAD)","author":"Wei"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT64416.2024.11113444"},{"key":"ref22","volume-title":"FPGA interchange format","author":"Kurc","year":"2024"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502356"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505434"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3406959"},{"key":"ref26","first-page":"1027","article-title":"k-means ++: The advantages of careful seeding","volume-title":"Proc. 18th Annu. ACM-SIAM Symp. Discrete Algorithms","author":"Arthur"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.00075"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00028"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11360509\/11075842.pdf?arnumber=11075842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T21:02:11Z","timestamp":1769115731000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11075842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2]]},"references-count":28,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3587534","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,2]]}}}