{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T21:24:22Z","timestamp":1771881862734,"version":"3.50.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T00:00:00Z","timestamp":1772323200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"ACCESS \u2013 AI Chip Center for Emerging Smart Systems, sponsored by InnoHK funding, Hong Kong SAR"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,3]]},"DOI":"10.1109\/tcad.2025.3596765","type":"journal-article","created":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T17:44:27Z","timestamp":1754588667000},"page":"1115-1128","source":"Crossref","is-referenced-by-count":1,"title":["Configurable Dataflow and Adaptive Mapping Optimization for Hybrid ReRAM and SRAM Compute-in-Memory Accelerator"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5908-8738","authenticated-orcid":false,"given":"Jingyu","family":"He","sequence":"first","affiliation":[{"name":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Sai Kung, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5747-9663","authenticated-orcid":false,"given":"Xiaomeng","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Sai Kung, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9459-0779","authenticated-orcid":false,"given":"Kunming","family":"Shao","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Sai Kung, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3885-4912","authenticated-orcid":false,"given":"Kwang-Ting","family":"Cheng","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Sai Kung, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8024-2637","authenticated-orcid":false,"given":"Chi-Ying","family":"Tsui","sequence":"additional","affiliation":[{"name":"Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Sai Kung, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","article-title":"X-CHANGR: Changing memristive crossbar mapping for mitigating line-resistance induced accuracy degradation in deep neural networks","author":"Agrawal","year":"2019","journal-title":"arXiv:1907.00285"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2020.2987605"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref5","first-page":"815","article-title":"MEC: Memory-efficient convolution for deep neural network","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Cho"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2905361"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3198413"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067610"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731715"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365788"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070992"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247750"},{"key":"ref14","first-page":"451","article-title":"NAX: Neural architecture and memristive xbar based accelerator co-design","volume-title":"Proc. 59th ACM\/IEEE Design Autom. Conf.","author":"Negi"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3140753"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3031290"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2018.8573527"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3272874"},{"key":"ref22","first-page":"6105","article-title":"EfficientNet: Rethinking model scaling for convolutional neural networks","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Tan"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067285"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-022-04992-8"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323889"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2296137"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830322"},{"key":"ref28","first-page":"1","article-title":"ReSCIM: Variation-resilient high weight-loading bandwidth in-memory computation based on fine-grained hybrid integration of multi-level ReRAM and SRAM cells","volume-title":"Proc. 41st IEEE\/ACM Int. Conf. Comput.-Aided Design","author":"Wang"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1038.\/s41586-020-1942-4"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067779"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11404293\/11119681.pdf?arnumber=11119681","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T20:48:03Z","timestamp":1771879683000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11119681\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,3]]},"references-count":30,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3596765","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,3]]}}}