{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T08:30:50Z","timestamp":1774341050811,"version":"3.50.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62374027"],"award-info":[{"award-number":["62374027"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,4]]},"DOI":"10.1109\/tcad.2025.3607152","type":"journal-article","created":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T17:45:57Z","timestamp":1757353557000},"page":"1625-1634","source":"Crossref","is-referenced-by-count":0,"title":["A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-6652-1859","authenticated-orcid":false,"given":"Xuerong","family":"Jia","sequence":"first","affiliation":[{"name":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, Shannxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7682-5987","authenticated-orcid":false,"given":"Song","family":"Wang","sequence":"additional","affiliation":[{"name":"Xi’an UniIC Semiconductors Company Ltd., Xi’an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8887-595X","authenticated-orcid":false,"given":"Yixin","family":"Guo","sequence":"additional","affiliation":[{"name":"Xi’an UniIC Semiconductors Company Ltd., Xi’an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7971-5986","authenticated-orcid":false,"given":"Fujun","family":"Bai","sequence":"additional","affiliation":[{"name":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, Shannxi, China"}]},{"given":"Bing","family":"Yu","sequence":"additional","affiliation":[{"name":"Xi’an UniIC Semiconductors Company Ltd., Xi’an, China"}]},{"given":"Xiyuan","family":"Feng","sequence":"additional","affiliation":[{"name":"Xi’an UniIC Semiconductors Company Ltd., Xi’an, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-0351-5259","authenticated-orcid":false,"given":"Yi","family":"Liu","sequence":"additional","affiliation":[{"name":"Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0805-5930","authenticated-orcid":false,"given":"Zhiwei","family":"Liu","sequence":"additional","affiliation":[{"name":"Center for Advanced Semiconductor and Integrated Micro-System, University of Electronic Science and Technology of China, Chengdu, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4002-9281","authenticated-orcid":false,"given":"Li","family":"Geng","sequence":"additional","affiliation":[{"name":"School of Microelectronics and Faculty of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, Shannxi, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0092-2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2022.3171862"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185427"},{"issue":"14","key":"ref5","doi-asserted-by":"crossref","first-page":"2340","DOI":"10.3390\/nano12142340","article-title":"Selective overview of 3D heterogeneity in CMOS","volume":"12","author":"Li","year":"2022","journal-title":"Nanomaterials"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831872"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424351"},{"key":"ref8","first-page":"6.6.1","article-title":"A stacked embedded DRAM array for LPDDR4\/4X using hybrid bonding 3D integration with 34 GB\/s\/1 Gb 0.88 pJ\/b logic-to-memory interface","author":"Fujun","year":"2020","journal-title":"IEDM Tech. Dig."},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2011.5898174"},{"issue":"17","key":"ref10","doi-asserted-by":"crossref","first-page":"2490","DOI":"10.3390\/nano13172490","article-title":"Cu-based thermocompression bonding and Cu\/dielectric hybrid bonding for three-dimensional integrated circuits (3D ICs) application","volume":"13","author":"Huang","year":"2023","journal-title":"Nanomaterials"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2015.2491308"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1016\/S0016-0032(10)90872-7","article-title":"The temperature coefficient of resistance of copper","volume":"170","author":"Dellinger","year":"1910","journal-title":"J. Franklin Inst."},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2027-6_52"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3178420"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.811978"},{"key":"ref17","first-page":"1","article-title":"HBM failure diagnosis on a high-frequency analog design with full-chip dynamic ESD simulation","volume-title":"Proc. Electr. Overstress\/Electrostatic Discharge Symp.","author":"Tong"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ipfa.2017.8060145"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2016.7592553"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2330365"},{"issue":"23","key":"ref21","doi-asserted-by":"crossref","first-page":"4250","DOI":"10.3390\/nano12234250","article-title":"Ultra-low-voltage-triggered silicon controlled rectifier ESD protection device for 2.5 V nano integrated circuit","volume":"12","author":"Chen","year":"2022","journal-title":"Nanomaterials"},{"issue":"10","key":"ref22","doi-asserted-by":"crossref","first-page":"1743","DOI":"10.3390\/nano12101743","article-title":"Silicon-controlled rectifier embedded diode for 7 nm FinFET process electrostatic discharge protection","volume":"12","author":"Zhu","year":"2022","journal-title":"Nanomaterials"},{"issue":"8","key":"ref23","doi-asserted-by":"crossref","first-page":"1426","DOI":"10.3390\/nano13081426","article-title":"Graphene-based ESD protection for future ICs","volume":"13","author":"Li","year":"2023","journal-title":"Nanomaterials"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.1995.478263"},{"key":"ref25","first-page":"1","article-title":"CDM protection of a 3D TSV memory IC with a 100 GB\/s wide I\/O data bus","volume-title":"Proc. Electr. Overstress\/Electrostatic Discharge Symp.","author":"Nagata"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2818707"},{"key":"ref27","volume-title":"Machine Model (MM)\u2014Don\u2019t Do It","year":"2025"},{"key":"ref28","first-page":"56","article-title":"Discontinuing use of the machine model for device ESD qualification","volume":"2012","author":"Duvvury","year":"2012","journal-title":"Compliance Mag."},{"key":"ref29","volume-title":"Industry Council on ESD Target Levels, Industry Council on ESD Target Levels White Paper 2: A Case for Lowering Component-Level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces","year":"2024"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.3390\/mi15050557"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/24050004"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11450487\/11153434.pdf?arnumber=11153434","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T05:16:46Z","timestamp":1774329406000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11153434\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4]]},"references-count":31,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3607152","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,4]]}}}