{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T08:31:43Z","timestamp":1774341103346,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T00:00:00Z","timestamp":1775001600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,4]]},"DOI":"10.1109\/tcad.2025.3608647","type":"journal-article","created":{"date-parts":[[2025,9,10]],"date-time":"2025-09-10T17:46:34Z","timestamp":1757526394000},"page":"1852-1866","source":"Crossref","is-referenced-by-count":0,"title":["Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0838-3355","authenticated-orcid":false,"given":"Oussama","family":"Oulkaid","sequence":"first","affiliation":[{"name":"Université Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8426-6516","authenticated-orcid":false,"given":"Bruno","family":"Ferres","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6054-8882","authenticated-orcid":false,"given":"Matthieu","family":"Moy","sequence":"additional","affiliation":[{"name":"Université Claude Bernard Lyon 1, CNRS, ENS de Lyon, Inria, LIP, UMR 5668, Lyon cedex 07, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3876-9125","authenticated-orcid":false,"given":"Pascal","family":"Raymond","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, Grenoble INP-Institute of Engineering, VERIMAG, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8482-1521","authenticated-orcid":false,"given":"Mehdi Khosravian","family":"Ghadikolaei","sequence":"additional","affiliation":[{"name":"Aniah, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Part 8: The 2022 Wilson Research Group Functional Verification Study\u2014Verification Horizons","year":"2022"},{"key":"ref2","volume-title":"Part 12: The 2022 Wilson Research Group Functional Verification Study\u2014Verification Horizons","year":"2022"},{"key":"ref3","article-title":"Formal methods for the verification of digital circuits","author":"Van Eijk","year":"1997"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546537"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270142"},{"key":"ref6","first-page":"1","article-title":"Case study: Power-aware IP and mixed-signal verification","volume-title":"Proc. DVCON","author":"Lang"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19941246"},{"key":"ref8","article-title":"SPICE (simulation program with integrated circuit emphasis)","author":"Nagel","year":"1973"},{"key":"ref9","first-page":"15","volume-title":"DC Analysis","author":"Kundert","year":"1995"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.3390\/app13042369"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/tc.1984.1676408"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2012.6339384"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-013-0107-x"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333694"},{"key":"ref15","first-page":"404","article-title":"Software check for power-down mode of analog circuits","volume-title":"Proc. 22nd Eur. Solid-State Circuits Conf.","author":"Blieck"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0140"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2015.7314812"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927102"},{"key":"ref19","volume-title":"Method of predicting electronic circuit floating gates","author":"Newcomb","year":"2012"},{"key":"ref20","volume-title":"Circuit states","author":"Newcomb","year":"2010"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.294"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2015.03.003"},{"key":"ref23","first-page":"1","article-title":"Using static voltage analysis and voltage-aware DRC to identify EOS and oxide breakdown reliability issues","volume-title":"Proc. 35th Electr. Overstress\/Electrostatic Discharge Symp.","author":"Hogan"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"ref25","volume-title":"5.11 The Junction Field-Effect Transistor (JFET)","author":"Sedra","year":"2010"},{"key":"ref26","volume-title":"HSPICE Reference Manual: MOSFET Models","year":"2013"},{"key":"ref27","article-title":"Comparison of level 1, 2 and 3 MOSFET\u2019s","author":"Patel","year":"2014"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1002\/0470863803"},{"key":"ref29","volume-title":"M. MOSFET","year":"2024"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1949.tb03645.x"},{"key":"ref31","article-title":"Measurements and analysis of current-voltage characteristic of a pn diode for an undergraduate physics laboratory","author":"Cataldo","year":"2016","journal-title":"arXiv:1608.05638"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137147"},{"key":"ref33","volume-title":"Power MOSFET Maximum Ratings","year":"2018"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11450487\/11156099.pdf?arnumber=11156099","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T05:16:56Z","timestamp":1774329416000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11156099\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4]]},"references-count":33,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3608647","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,4]]}}}