{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:03:02Z","timestamp":1780444982283,"version":"3.54.1"},"reference-count":63,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660300"],"award-info":[{"award-number":["XDB0660300"]}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660301"],"award-info":[{"award-number":["XDB0660301"]}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660302"],"award-info":[{"award-number":["XDB0660302"]}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660200"],"award-info":[{"award-number":["XDB0660200"]}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660201"],"award-info":[{"award-number":["XDB0660201"]}]},{"name":"Strategic Priority Research Program of the Chinese Academy of Sciences","award":["XDB0660202"],"award-info":[{"award-number":["XDB0660202"]}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["U22A2028"],"award-info":[{"award-number":["U22A2028"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["6240073476"],"award-info":[{"award-number":["6240073476"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62222214"],"award-info":[{"award-number":["62222214"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62341411"],"award-info":[{"award-number":["62341411"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62302478"],"award-info":[{"award-number":["62302478"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62302483"],"award-info":[{"award-number":["62302483"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62402477"],"award-info":[{"award-number":["62402477"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"crossref","award":["62372436"],"award-info":[{"award-number":["62372436"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"name":"CAS Project for Young Scientists in Basic Research","award":["YSBR-029"],"award-info":[{"award-number":["YSBR-029"]}]},{"DOI":"10.13039\/501100002367","name":"Youth Innovation Promotion Association CAS","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,5]]},"DOI":"10.1109\/tcad.2025.3617851","type":"journal-article","created":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T17:25:37Z","timestamp":1759512337000},"page":"2362-2375","source":"Crossref","is-referenced-by-count":1,"title":["AGON: Automated Design Framework for Customizing Processors From ISA Documents"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-2215-4892","authenticated-orcid":false,"given":"Chongxiao","family":"Li","sequence":"first","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2370-0072","authenticated-orcid":false,"given":"Di","family":"Huang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8267-9824","authenticated-orcid":false,"given":"Pengwei","family":"Jin","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-4204-0686","authenticated-orcid":false,"given":"Tianyun","family":"Ma","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0873-3471","authenticated-orcid":false,"given":"Husheng","family":"Han","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6291-0531","authenticated-orcid":false,"given":"Shuyao","family":"Cheng","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9823-2573","authenticated-orcid":false,"given":"Yifan","family":"Hao","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5503-4457","authenticated-orcid":false,"given":"Yongwei","family":"Zhao","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guanglin","family":"Xu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7603-4210","authenticated-orcid":false,"given":"Zidong","family":"Du","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8691-8549","authenticated-orcid":false,"given":"Rui","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7748-7967","authenticated-orcid":false,"given":"Xiaqing","family":"Li","sequence":"additional","affiliation":[{"name":"Key Laboratory of Big Data and Artificial Intelligence in Transportation, Ministry of Education, and the School of Computer Science and Technology, Beijing Jiaotong University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7775-2724","authenticated-orcid":false,"given":"Yuanbo","family":"Wen","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9979-0561","authenticated-orcid":false,"given":"Xing","family":"Hu","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2530-5874","authenticated-orcid":false,"given":"Qi","family":"Guo","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3050785"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311282"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2007.4511249"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E95.A.2373"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.844109"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.367"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref8","volume-title":"SpinalHDL\/SpinalHDL: Scala Based HDL","year":"2024"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00080"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075913"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834439"},{"key":"ref12","article-title":"RTLLM: An open-source benchmark for design RTL generation with large language model","author":"Lu","year":"2023","journal-title":"arXiv:2308.05345"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/2023.emnlp-main.151"},{"key":"ref14","first-page":"56181","article-title":"RepoBench: Benchmarking repository-level code auto-completion systems","volume-title":"Proc. 12th Int. Conf. Learn. Represent.","author":"Liu"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691810"},{"key":"ref16","volume-title":"RISCV\/RISCV-Crypto: RISC-V Cryptography Extensions Standardisation Work","year":"2023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247872"},{"key":"ref18","volume-title":"RISCV\/RISCV-V-Spec: RISC-V V Vector Extension","year":"2022"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HOST49136.2021.9702275"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3092627.3092629"},{"key":"ref21","article-title":"DuVisor: A user-level hypervisor through delegated virtualization","author":"Chen","year":"2022","journal-title":"arXiv:2201.09652"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HCS52781.2021.9567229"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3242897"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/PATMOS.2017.8106976"},{"key":"ref25","first-page":"1","article-title":"Sonicboom: The 3rd generation Berkeley out-of-order machine","volume-title":"Proc. 4th Workshop Comput. Archit. Res. RISC-V","volume":"5","author":"Zhao"},{"key":"ref26","article-title":"The rocket chip generator","author":"Asanovic","year":"2016"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299874"},{"key":"ref29","article-title":"ChipGPT: How far are we from natural language hardware design","author":"Chang","year":"2023","journal-title":"arXiv:2305.14019"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137086"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323812"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657356"},{"key":"ref33","first-page":"40145","article-title":"BetterV: Controlled verilog generation with discriminative guidance","volume-title":"Proc. 41st Int. Conf. Mach. Learn.","author":"Pei"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2025.3604320"},{"key":"ref35","article-title":"QiMeng-CodeV-r1: Reasoning-enhanced verilog generation","author":"Zhu","year":"2025","journal-title":"arXiv:2505.24183"},{"key":"ref36","first-page":"1","article-title":"StarCoder: May the source be with you!","volume-title":"Proc. Trans. Mach. Learn. Res.","author":"Li"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/2024.findings-acl.49"},{"key":"ref38","article-title":"Evaluating large language models trained on code","author":"Chen","year":"2021","journal-title":"arXiv:2107.03374"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3735638"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1162\/tacl_a_00638"},{"key":"ref41","article-title":"RTLCoder: Outperforming GPT-3.5 in design RTL generation with our open-source dataset and lightweight solution","author":"Liu","year":"2023","journal-title":"arXiv:2312.08617"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref43","article-title":"RealBench: Benchmarking verilog generation models with real-world IP designs","author":"Jin","year":"2025","journal-title":"arXiv:2507.16200"},{"key":"ref44","volume-title":"Opencores: Open Source IP-Cores","year":"2025"},{"key":"ref45","article-title":"LLM4EDA: Emerging progress in large language models for electronic design automation","author":"Zhong","year":"2023","journal-title":"arXiv:2401.12224"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3494523"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/12.919279"},{"key":"ref48","first-page":"469","article-title":"McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures","volume-title":"Proc. 42nd Annu. IEEE\/ACM Int. Symp. Microarchitecture (MICRO)","author":"Li"},{"key":"ref49","volume-title":"RISCV\/RISCV-P-Spec: RISC-V Packed SIMD Extension","year":"2022"},{"key":"ref50","first-page":"1877","article-title":"Language models are few-shot learners","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Brown"},{"key":"ref51","article-title":"Teaching large language models to self-debug","author":"Chen","year":"2023","journal-title":"arXiv:2304.05128"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1126\/science.abq1158"},{"key":"ref53","volume-title":"Nuclei Microcontroller Software Interface Standard","year":"2023"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1016\/B978-012374287-2.50007-0"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.994928"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3658493"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ECBS.2012.49"},{"key":"ref58","first-page":"1","article-title":"Rapid generation of high-quality RISC-V processors from functional instruction set specifications","volume-title":"Proc. 56th ACM\/IEEE Design Autom. Conf. (DAC)","author":"Liu"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/3290384"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/3620666.3651375"},{"key":"ref61","article-title":"ChipNeMo: Domain-adapted LLMs for chip design","author":"Liu","year":"2023","journal-title":"arXiv:2311.00176"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/tifs.2024.3372809"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11493579\/11192497.pdf?arnumber=11192497","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T19:59:14Z","timestamp":1776974354000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11192497\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5]]},"references-count":63,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3617851","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,5]]}}}