{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T21:01:46Z","timestamp":1776978106131,"version":"3.51.4"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2026,5]]},"DOI":"10.1109\/tcad.2025.3618934","type":"journal-article","created":{"date-parts":[[2025,10,7]],"date-time":"2025-10-07T17:42:47Z","timestamp":1759858967000},"page":"2395-2408","source":"Crossref","is-referenced-by-count":0,"title":["A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication"],"prefix":"10.1109","volume":"45","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-1620-0096","authenticated-orcid":false,"given":"Yifan","family":"Song","sequence":"first","affiliation":[{"name":"State Key Laboratory of Integrated Circuits and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0817-261X","authenticated-orcid":false,"given":"Yuxuan","family":"Qiao","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Circuits and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0132-1461","authenticated-orcid":false,"given":"Changxu","family":"Liu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Circuits and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yifei","family":"Feng","sequence":"additional","affiliation":[{"name":"College of Computer Science and Artificial Intelligence, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junjie","family":"Zuo","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Circuits and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1918-4762","authenticated-orcid":false,"given":"Baoyu","family":"Fan","sequence":"additional","affiliation":[{"name":"Department of System Architecture Research, IEIT Systems Company Ltd., Jinan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2164-8175","authenticated-orcid":false,"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Integrated Circuits and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref2","article-title":"Deep learning inference in Facebook data centers: Characterization, performance optimizations and hardware implications","author":"Park","year":"2018","journal-title":"arXiv:1811.09886"},{"issue":"3","key":"ref3","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1016\/j.eng.2020.01.007","article-title":"A survey of accelerator architectures for deep neural networks","volume":"6","author":"Chen","year":"2020","journal-title":"Engineering"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1906.00091"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS50870.2020.9159704"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2019.2915656"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTS50974.2021.9441050"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00076"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW.2017.61"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637562"},{"key":"ref13","first-page":"798","article-title":"Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE)","author":"Sahoo"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2018.8368656"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3236875"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3051841"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/12.21144"},{"issue":"2","key":"ref18","doi-asserted-by":"crossref","first-page":"338","DOI":"10.3390\/electronics9020338","article-title":"Efficient systolic-array redundancy architecture for offline\/online repair","volume":"9","author":"Cho","year":"2020","journal-title":"Electronics"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3421563"},{"key":"ref20","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"Han","year":"2015","journal-title":"arXiv:1510.00149"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52729.2023.01544"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCT56141.2022.10073392"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937284"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3061394"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323775"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676663"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ATS49688.2020.9301581"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676475"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00095"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ATS64447.2024.10915421"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISEDA65950.2025.11100433"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/RSM52397.2021.9511602"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106812"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CAHPC.2018.8645906"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref36","volume-title":"Mnist Handwritten Digit Database","author":"LeCun","year":"2010"},{"key":"ref37","first-page":"84","article-title":"ImageNet classification with deep convolutional neural networks","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","volume":"60","author":"Krizhevsky"},{"key":"ref38","article-title":"Learning multiple layers of features from tiny images","author":"Krizhevsky","year":"2009"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD56317.2022.00086"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/11493579\/11195802.pdf?arnumber=11195802","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T19:59:22Z","timestamp":1776974362000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11195802\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5]]},"references-count":39,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3618934","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,5]]}}}