{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T18:09:34Z","timestamp":1648922974315},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T00:00:00Z","timestamp":1288569600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Consumer Electron."],"published-print":{"date-parts":[[2010,11]]},"DOI":"10.1109\/tce.2010.5681119","type":"journal-article","created":{"date-parts":[[2011,1,10]],"date-time":"2011-01-10T21:14:06Z","timestamp":1294694046000},"page":"2400-2405","source":"Crossref","is-referenced-by-count":3,"title":["A 90\u00b0 phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface"],"prefix":"10.1109","volume":"56","author":[{"given":"Dong","family":"Jung","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyung","family":"Ryu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seong-Ook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2010.5505992"},{"key":"ref11","article-title":"A 1.35V 4.3GB\/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application","author":"jeong","year":"2009","journal-title":"ISSCC Digest of Technical Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405755"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e88-c.4.773"},{"key":"ref14","first-page":"379","article-title":"Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb\/s\/pin double data rate SDRAM","author":"jang","year":"2004","journal-title":"IEEE European Solid-State Circuits Conference"},{"key":"ref4","year":"2009","journal-title":"ARM Cortex A8 Processor"},{"key":"ref3","year":"2007","journal-title":"ARM Cortex-A8 Processor Product Brief"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004523"},{"key":"ref5","article-title":"A 4.3GB\/s mobile memory interface with power-efficient bandwidth scaling","author":"palmer","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5278024"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2004.1277872"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2007.4341593"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/30.920475"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2009.5373819"}],"container-title":["IEEE Transactions on Consumer Electronics"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/30\/5681060\/05681119.pdf?arnumber=5681119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:01:42Z","timestamp":1642003302000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5681119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11]]},"references-count":14,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tce.2010.5681119","relation":{},"ISSN":["0098-3063"],"issn-type":[{"value":"0098-3063","type":"print"}],"subject":[],"published":{"date-parts":[[2010,11]]}}}