{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T19:48:56Z","timestamp":1694634536101},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2008,10,1]],"date-time":"2008-10-01T00:00:00Z","timestamp":1222819200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/tcsi.2008.920096","type":"journal-article","created":{"date-parts":[[2008,11,5]],"date-time":"2008-11-05T14:59:42Z","timestamp":1225897182000},"page":"2514-2524","source":"Crossref","is-referenced-by-count":11,"title":["10-Gb\/s Inductorless CDRs With Digital Frequency Calibration"],"prefix":"10.1109","volume":"55","author":[{"family":"Che-Fu Liang","sequence":"first","affiliation":[]},{"family":"Hong-Lin Chu","sequence":"additional","affiliation":[]},{"family":"Shen-Iuan Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320828"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961113"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806284"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883334"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/50.350582"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1995.535269"},{"key":"ref6","first-page":"3288","article-title":"novel 622 mb\/s burst-mode clock and data recovery circuits with muxed oscillators","volume":"e86 b","author":"kim","year":"2003","journal-title":"IEICE Trans Commun"},{"key":"ref5","first-page":"1423","article-title":"155-mb\/s burst-mode clock recovery circuit using the jitter reduction technique","volume":"e86 b","author":"hwang","year":"2003","journal-title":"IEICE Trans Commun"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234211"},{"key":"ref7","first-page":"3069","article-title":"1.25\/2.5-gb\/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-m cmos","author":"han","year":"2006","journal-title":"IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1993.280066"},{"key":"ref1","year":"2003","journal-title":"G 984 2 Gigabit-Capable Passive Optical Networks (GPON) Physical Media Dependent (PMD) Layer"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493952"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/4663192\/04469658.pdf?arnumber=4469658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T15:41:19Z","timestamp":1638200479000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4469658\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":13,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2008.920096","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,10]]}}}