{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,30]],"date-time":"2024-12-30T18:18:05Z","timestamp":1735582685413},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/tcsi.2009.2015720","type":"journal-article","created":{"date-parts":[[2009,2,26]],"date-time":"2009-02-26T14:39:18Z","timestamp":1235659158000},"page":"236-248","source":"Crossref","is-referenced-by-count":13,"title":["Exact Time-Domain Second-Order Adjoint-Sensitivity Computation for Linear Circuit Analysis and Optimization"],"prefix":"10.1109","volume":"57","author":[{"family":"Xiaoji Ye","sequence":"first","affiliation":[]},{"family":"Peng Li","sequence":"additional","affiliation":[]},{"given":"F.Y.","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"913","DOI":"10.1109\/TVLSI.2007.900738","article-title":"fast variational interconnect delay and slew computation using quadratic models","volume":"15","author":"ye","year":"2007","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929760"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/157485.164653","article-title":"reliable non-zero skew clock trees using wire width optimization","author":"pullela","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/66.843637"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643521"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1991.164097"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809658"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.736569"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.76947"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TAP.2004.832313"},{"key":"ref2","author":"pillage","year":"1998","journal-title":"Electronic Circuit and System Simulation Methods"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1969.1082965"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.68404"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5382607\/04785481.pdf?arnumber=4785481","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:20Z","timestamp":1633913060000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4785481\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2009.2015720","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,1]]}}}