{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:30:42Z","timestamp":1765355442315},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2010,1,1]],"date-time":"2010-01-01T00:00:00Z","timestamp":1262304000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,1]]},"DOI":"10.1109\/tcsi.2009.2019396","type":"journal-article","created":{"date-parts":[[2009,3,30]],"date-time":"2009-03-30T14:06:42Z","timestamp":1238422002000},"page":"31-43","source":"Crossref","is-referenced-by-count":47,"title":["Modeling $R{-}2R$ Segmented-Ladder DACs"],"prefix":"10.1109","volume":"57","author":[{"given":"D.","family":"Marche","sequence":"first","affiliation":[]},{"given":"Y.","family":"Savaria","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/el:19800660"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1985.1085641"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008510"},{"key":"ref13","year":"1981","journal-title":"Digital to Analog Conversion Circuit Including Compensation FET's"},{"key":"ref14","year":"1990","journal-title":"Electronic Analog-to-Digital Converters"},{"key":"ref15","year":"1992","journal-title":"D\/A Converter for Minimizing Nonlinear Error"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/S0169-4332(01)00622-5"},{"key":"ref4","first-page":"4779","article-title":"a digitally calibrated <ref_formula> <tex notation=\"tex\">$r{-}2r$<\/tex><\/ref_formula> ladder architecture for high performance digital-to-analog converters","author":"karadimas","year":"2006","journal-title":"Proc ISCAS"},{"key":"ref3","year":"2004","journal-title":"AD5554 Precision QUAD 14-Bit D\/A Converter"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/81.828565"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.920152"},{"key":"ref8","year":"2006","journal-title":"Compensated inverted ladder and compensation technique therefor"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/19.982980"},{"key":"ref2","year":"1998","journal-title":"Ltc159114-Bit Parallel Low Glitch Multiplying DAC With 4-Quadrant Resistors"},{"key":"ref1","year":"1986","journal-title":"Analog\/Digital Conversion Handbook"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1983.1085332"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5382607\/04806048.pdf?arnumber=4806048","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:35Z","timestamp":1633909895000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4806048\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":16,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2009.2019396","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,1]]}}}