{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:48:45Z","timestamp":1759146525079},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2010,6,1]],"date-time":"2010-06-01T00:00:00Z","timestamp":1275350400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/tcsi.2009.2030113","type":"journal-article","created":{"date-parts":[[2010,1,8]],"date-time":"2010-01-08T19:14:10Z","timestamp":1262978050000},"page":"1273-1286","source":"Crossref","is-referenced-by-count":41,"title":["Flip-Flop Energy\/Performance Versus Clock Slope and Impact on the Clock Network Design"],"prefix":"10.1109","volume":"57","author":[{"given":"Massimo","family":"Alioto","sequence":"first","affiliation":[]},{"given":"Elio","family":"Consoli","sequence":"additional","affiliation":[]},{"given":"Gaetano","family":"Palumbo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/92.974902"},{"key":"ref38","author":"weste","year":"2004","journal-title":"CMOS VLSI Design A Circuits and System Perspective"},{"key":"ref33","first-page":"399","article-title":"a low power simmetrically pulsed dual edge-triggered flip-flop","author":"nedovic","year":"2002","journal-title":"Proc ESSCC"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547536"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/4.938376"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234326"},{"key":"ref37","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2033538"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826192"},{"key":"ref34","first-page":"147","article-title":"comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors","author":"tschanz","year":"2001","journal-title":"Proc ISLPED"},{"key":"ref10","author":"harris","year":"2000","journal-title":"Skew-Tolerant Circuit Design"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887809"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.293119"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628871"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217577"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/rd.475.0567"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.896516"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1002\/0471723703"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.896691"},{"key":"ref18","author":"sutherland","year":"1998","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.753687"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.895514"},{"key":"ref27","first-page":"477","article-title":"low power and high speed explicit-pulsed flip-flops","author":"zhao","year":"2002","journal-title":"Proc MSCS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.844302"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/81.296331"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.845191"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/82.592586"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4684-8440-3_6"},{"key":"ref7","first-page":"207","author":"partovi","year":"2001","journal-title":"Design of High-Performance Microprocessor Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.726547"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.668981"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313902"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/43.559336"},{"key":"ref46","year":"2005","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231847"},{"key":"ref22","first-page":"52","article-title":"analysis and design of low-energy flip-flops","author":"markovic","year":"2001","journal-title":"Proc ISPLED"},{"key":"ref48","year":"2008","journal-title":"Berkeley Predictive Technology Model (BPTM)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-34047-0"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1996.488543"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2015455"},{"key":"ref23","year":"2003","journal-title":"Transmission-gate based flip-flop"},{"key":"ref41","author":"orshansky","year":"2008","journal-title":"Design for Manufacturability and Statistical Design"},{"key":"ref26","first-page":"803","article-title":"conditional techniques for low power consumption flip-flops","volume":"2","author":"nedovic","year":"2001","journal-title":"Proc ICECS"},{"key":"ref44","first-page":"334","article-title":"overview of low-power ulsi circuit techniques","volume":"e78 c","author":"kuroda","year":"1995","journal-title":"T IEICED"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.881196"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1002\/0471653829"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5482395\/05371919.pdf?arnumber=5371919","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:59:24Z","timestamp":1633910364000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5371919\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":48,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2009.2030113","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,6]]}}}