{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:18:19Z","timestamp":1767183499863},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2010,7,1]],"date-time":"2010-07-01T00:00:00Z","timestamp":1277942400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,7]]},"DOI":"10.1109\/tcsi.2009.2035417","type":"journal-article","created":{"date-parts":[[2010,1,20]],"date-time":"2010-01-20T14:22:20Z","timestamp":1263997340000},"page":"1549-1558","source":"Crossref","is-referenced-by-count":23,"title":["A Built-In-Test Circuit for RF Differential Low Noise Amplifiers"],"prefix":"10.1109","volume":"57","author":[{"given":"Lambros E","family":"Dermentzoglou","sequence":"first","affiliation":[]},{"given":"Angela","family":"Arapoyanni","sequence":"additional","affiliation":[]},{"given":"Yiorgos","family":"Tsiatouhas","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2005.01.002"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.06.0104.0122"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2006.379805"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1261064"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2005.52"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.87"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2005.1489898"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2008.921293"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.918207"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743212"},{"key":"ref28","first-page":"31","article-title":"novel defect testing of rf front end using input matching measurement","author":"ryu","year":"2003","journal-title":"Proc 9th IEEE Int Mixed-Signal Testing Workshop"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998268"},{"key":"ref27","author":"vinnakota","year":"1998","journal-title":"Analog and Mixed-Signal Test"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.986428"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/54.386008"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584001"},{"key":"ref5","author":"bushnell","year":"2001","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"220","DOI":"10.1109\/DFTVS.2004.1347843","article-title":"mixed loop-back bist for rf digital transceivers","author":"dabrowski","year":"2004","journal-title":"Proc Int Symp Defect Fault Tolerance in VLSI Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343762"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.828819"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2005.855091"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/82.728852"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-46547-2"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2007.4511191"},{"key":"ref21","first-page":"714","article-title":"a design for testability technique for differential rf low noise amplifiers","author":"dermentzoglou","year":"2005","journal-title":"Proc Conf Des Circuits Integr Syst (DCIS)"},{"key":"ref24","author":"lee","year":"1998","journal-title":"The Design of CMOS Radio-Frequency Integrated Circuits"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/92.335020"},{"key":"ref26","author":"hastings","year":"2005","journal-title":"The Art of Analog Layout"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCDCS.2000.869874"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5512812\/05378476.pdf?arnumber=5378476","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:00:35Z","timestamp":1633914035000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5378476\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,7]]},"references-count":29,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2009.2035417","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,7]]}}}