{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,17]],"date-time":"2026-01-17T18:04:43Z","timestamp":1768673083061,"version":"3.49.0"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2010,10,1]],"date-time":"2010-10-01T00:00:00Z","timestamp":1285891200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1109\/tcsi.2010.2046966","type":"journal-article","created":{"date-parts":[[2010,5,12]],"date-time":"2010-05-12T19:58:02Z","timestamp":1273694282000},"page":"2718-2728","source":"Crossref","is-referenced-by-count":120,"title":["Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory"],"prefix":"10.1109","volume":"57","author":[{"given":"Guiqiang","family":"Dong","sequence":"first","affiliation":[]},{"given":"Shu","family":"Li","sequence":"additional","affiliation":[]},{"given":"Tong","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1089733.1089735"},{"key":"ref31","author":"may","year":"2000","journal-title":"Parallel I\/O for High Performance Computing"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511606267"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/WMED.2009.4816143"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3136-4"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1272","DOI":"10.1109\/TCSI.2008.2008479","article-title":"novel fext cancellation and equalization for high speed ethernet transmission","volume":"56","author":"chen","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.883168"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.822552"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.921062"},{"key":"ref16","year":"2009","journal-title":"Compensating for coupling based on sensing a neighbor using coupling"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.475701"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811702"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.888299"},{"key":"ref28","year":"2007","journal-title":"Deep Wordline Trench to Shield Cross Coupling Between Adjacent Cells for Scaled NAND"},{"key":"ref4","first-page":"240","article-title":"a 48 nm 32 gb 8-level nand flash memory with 5.5 mb\/s program throughput","author":"chang","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref27","year":"2008","journal-title":"Shield plate for limiting cross coupling between floating gates"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007154"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977400"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1002\/0471200611"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917559"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2008.4530774"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558857"},{"key":"ref2","first-page":"242","article-title":"a 113 <ref_formula><tex notation=\"tex\">$\\hbox{mm}^{2}$<\/tex> <\/ref_formula> 32 gb 3 b\/cell nand flash memory","author":"futatsuyama","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NVSMW.2007.4290561"},{"key":"ref1","first-page":"430","article-title":"a 120 <ref_formula><tex notation=\"tex\">$\\hbox{mm}^{2}$<\/tex><\/ref_formula> 16 gb 4-mlc nand flash memory with 43 nm cmos technology","author":"kanda","year":"2008","journal-title":"Proc IEEE ISSCC"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917558"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007152"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007154"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.499738"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/55.998871"},{"key":"ref26","year":"2007","journal-title":"Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342710"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5596209\/05460923.pdf?arnumber=5460923","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:02Z","timestamp":1633913042000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5460923\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10]]},"references-count":32,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2010.2046966","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,10]]}}}