{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:24:23Z","timestamp":1773246263668,"version":"3.50.1"},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/tcsi.2010.2071590","type":"journal-article","created":{"date-parts":[[2010,9,29]],"date-time":"2010-09-29T15:45:38Z","timestamp":1285775138000},"page":"2301-2311","source":"Crossref","is-referenced-by-count":29,"title":["ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies"],"prefix":"10.1109","volume":"57","author":[{"given":"Shuqing","family":"Cao","sequence":"first","affiliation":[]},{"given":"Jung-Hoon","family":"Chun","sequence":"additional","affiliation":[]},{"given":"Stephen G.","family":"Beebe","sequence":"additional","affiliation":[]},{"given":"Robert W.","family":"Dutton","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"crossref","first-page":"933","DOI":"10.1109\/TCSI.2009.2015185","article-title":"design of an esd-protected ultra-wideband lna in nanoscale cmos for full-band mobile tv tuners","volume":"56","author":"mak","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref38","doi-asserted-by":"crossref","first-page":"1026","DOI":"10.1109\/TCSII.2008.925661","article-title":"a scalable digitalized buffer for gigabit i\/o","volume":"55","author":"lu","year":"2008","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(98)00172-3"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346971"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2008.4656335"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2007.4401750"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.920096"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2009.5173316"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2019164"},{"key":"ref34","first-page":"179","article-title":"Design and Characterization of a Multi-RC-triggered MOSFET-based Power Clamp for on-chip ESD Protection","author":"junjun li","year":"2006","journal-title":"2006 Electrical Overstress\/Electrostatic Discharge Symposium eos\/esd"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.846824"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2015178"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.1996.865156"},{"key":"ref2","first-page":"1","article-title":"technology scaling of advanced bulk cmos on-chip esd protection down to the 32 nm node","author":"li","year":"2009","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796688"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/55.622511"},{"key":"ref22","first-page":"4a.2-1","article-title":"Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100 nm bulk CMOS technologies","author":"li","year":"2007","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref21","first-page":"88","article-title":"a scalable compact model of interconnects self heating in cmos technology","author":"manouvrier","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref24","first-page":"228","article-title":"capacitance investigation of diode and ggnmos for esd protection of high frequency circuits in 45 nm soi cmos technologies","author":"li","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref23","first-page":"312","article-title":"esd protection using grounded gate, gate non-silicided (gg-gns) esd nfets in 45 nm soi technology","author":"mitra","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2245-4"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9106-5"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2006.11.007"},{"key":"ref51","first-page":"4a.1-1","article-title":"T-diodes—A novel plug-and-play wideband RF circuit ESD protection methodology","author":"linten","year":"2007","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref59","first-page":"183","article-title":"influence of cdm tester plate size on discharge current","author":"jahanzeb","year":"2009","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref58","first-page":"325","article-title":"CDM analysis on 65nm CMOS: Pitfalls when correlating results between IO test chips and product level","author":"teruo suzuki","year":"2008","journal-title":"EOS\/ESD 2008 - 2008 30th Electrical Overstress\/Electrostatic Discharge Symposium EOS\/ESD"},{"key":"ref57","year":"2009","journal-title":"White Paper 2 A case for lowering component level CDM ESD specifications and requirements"},{"key":"ref56","first-page":"115","article-title":"wafer-level charged device model testing","author":"chou","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2007.369911"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2007.4401765"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2009.10.006"},{"key":"ref52","author":"chun","year":"2006","journal-title":"ESD protection circuits for advanced CMOS technologies"},{"key":"ref10","first-page":"235","article-title":"esd device design strategy for high speed i\/o in 45 nm soi technology","author":"cao","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.05.009"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2028592"},{"key":"ref12","first-page":"91","article-title":"cdm protection design for cmos applications using rc-triggered rail clamps","author":"stockinger","year":"2009","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2039524"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2010586"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2007.369872"},{"key":"ref16","first-page":"50","article-title":"voltage clamping requirements for esd protection of inputs in 90 nm cmos technology","author":"lee","year":"2008","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/EOSESD.2007.4401771"},{"key":"ref18","first-page":"196","article-title":"esd time-domain characterization of high-k gate dielectric in a 32 nm cmos technology","author":"sarro","year":"2009","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref19","first-page":"1","article-title":"investigation on output driver with stacked devices for esd design window engineering","author":"cao","year":"2010","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1002\/9780470747254","author":"voldman","year":"2009","journal-title":"ESD Failure Mechanisms and Models"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280727"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/0470846054"},{"key":"ref5","first-page":"1","article-title":"analysis of esd protection components in 65 nm cmos technology: scaling perspective and impact on esd design window","author":"boselli","year":"2005","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1002\/0470033479"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MNANO.2009.934212"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.5573\/JSTS.2009.9.4.198"},{"key":"ref9","year":"2008","journal-title":"Recommended ESD target levels for HBM\/MM qualification"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818568"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.835639"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2023772"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.801257"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.922444"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.910968"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/55.852960"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1002\/0470061405"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5592146\/05582163.pdf?arnumber=5582163","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,3]],"date-time":"2023-06-03T14:49:48Z","timestamp":1685803788000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5582163\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":59,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2010.2071590","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}