{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T01:23:31Z","timestamp":1764811411280},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/tcsi.2010.2073790","type":"journal-article","created":{"date-parts":[[2010,12,11]],"date-time":"2010-12-11T13:42:49Z","timestamp":1292074969000},"page":"3055-3063","source":"Crossref","is-referenced-by-count":10,"title":["Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects"],"prefix":"10.1109","volume":"57","author":[{"given":"Ashok","family":"Narasimhan","sequence":"first","affiliation":[]},{"given":"Ramalingam","family":"Sridhar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120932"},{"key":"ref10","first-page":"131","article-title":"a probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations","author":"wason","year":"2005","journal-title":"Proc Int Symp Low Power Electron Des (ISLPED)"},{"key":"ref11","first-page":"101","article-title":"delay and power expressions for a cmos inverter driving a resistive-capacitive load","author":"adler","year":"1996","journal-title":"IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.658636"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.705287"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/16.75219"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/16.249433"},{"key":"ref17","first-page":"512","article-title":"modeling the driving-point characteristic of resistive interconnect for accurate delay estimation","author":"o'brien","year":"1989","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"648","DOI":"10.1109\/ISQED.2005.10","article-title":"a more effective <formula formulatype=\"inline\"><tex notation=\"tex\">$c_{eff}$<\/tex> <\/formula>","author":"nassif","year":"2005","journal-title":"Proc Int Symp Quality Electron Des"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863750"},{"key":"ref28","first-page":"174","article-title":"process variation aware clock tree routing","author":"lu","year":"2005","journal-title":"Proc Int Symp Phys Des (ISPD)"},{"key":"ref3","first-page":"568","article-title":"simultaneous analytic area and power optimization for repeater insertion","author":"garcea","year":"2003","journal-title":"Proc Int Conf Comput Aided Design (ICCAD)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466235"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954689"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/81.886981"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/157485.164653","article-title":"reliable non-zero skew clock trees using wire width optimization","author":"pullela","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.114"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.910538"},{"key":"ref2","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"338","DOI":"10.1145\/1278480.1278567","article-title":"fast min-cost buffer insertion under process variations","author":"ruiming chen","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref1","year":"2009","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852648"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2006.1648685"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118379"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120932"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922263"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.66"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5667090\/05658174.pdf?arnumber=5658174","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:46:35Z","timestamp":1633913195000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5658174\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":30,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2010.2073790","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}