{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T21:38:23Z","timestamp":1769549903856,"version":"3.49.0"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2011,6,1]],"date-time":"2011-06-01T00:00:00Z","timestamp":1306886400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/tcsi.2010.2103154","type":"journal-article","created":{"date-parts":[[2011,1,28]],"date-time":"2011-01-28T19:47:54Z","timestamp":1296244074000},"page":"1252-1263","source":"Crossref","is-referenced-by-count":80,"title":["An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS"],"prefix":"10.1109","volume":"58","author":[{"given":"Do","family":"Anh-Tuan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeremy Yung Shern","family":"Low","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joshua Yung Lih","family":"Low","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhi-Hui","family":"Kong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoliang","family":"Tan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kiat-Seng","family":"Yeo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1452","article-title":"Low power and robust 7T dual-vt SRAM circuit","author":"tawfik","year":"2008","journal-title":"Proc ISCAS"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2008.4616913"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.12"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405674"},{"key":"ref15","first-page":"2517","article-title":"45 nm low-power embedded pseudo-sram with ecc-based auto-adjusted self-refresh scheme","author":"suk-soo","year":"2009","journal-title":"Proc ISCAS"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494075"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.888767"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118476"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692513"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.877276"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016633"},{"key":"ref8","first-page":"3018","article-title":"Comparison of dual-vt configurations of SRAM cell considering process-induced vt variations","author":"jungseob","year":"2007","journal-title":"Proc ISCAS"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS.2008.4695924"},{"key":"ref2","first-page":"659","article-title":"A 0.56-V 128 kb 10T SRAM using column line assist (CLA) scheme","author":"okumura","year":"2009","journal-title":"Proc ISQED"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2007.4488015"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542171"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"986","DOI":"10.1109\/TCSII.2008.2001965","article-title":"Hybrid-mode SRAM sense amplifiers: New approach on transistor sizing","volume":"55","author":"do","year":"2008","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/5773659\/05701786.pdf?arnumber=5701786","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:58Z","timestamp":1633909618000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5701786\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":22,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2010.2103154","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,6]]}}}