{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T19:50:33Z","timestamp":1648583433108},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/tcsi.2011.2157742","type":"journal-article","created":{"date-parts":[[2011,7,11]],"date-time":"2011-07-11T16:12:30Z","timestamp":1310400750000},"page":"2808-2815","source":"Crossref","is-referenced-by-count":0,"title":["Sinusoidal Clock Sampling for Multigigahertz ADCs"],"prefix":"10.1109","volume":"58","author":[{"given":"Rui","family":"Bai","sequence":"first","affiliation":[]},{"given":"Jingguang","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Lingli","family":"Xia","sequence":"additional","affiliation":[]},{"given":"Feng","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Zongren","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Weiwu","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Chiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"razavi","year":"1995","journal-title":"Principles of Data Conversion System Design"},{"key":"ref11","first-page":"272","article-title":"A 20 Gb\/s <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$0.13~\\mu \\hbox{m}$<\/tex><\/formula> CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer","author":"chiang","year":"2004","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.75067"},{"key":"ref13","article-title":"High-speed ADC building blocks in 90 nm CMOS","author":"grozing","year":"2006","journal-title":"4th Joint Symp Opto- and Microelectron Devices Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040116"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320890"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342767"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585934"},{"key":"ref18","first-page":"268","article-title":"A 7.5-GS\/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65 nm CMOS","author":"chung","year":"2009","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405716"},{"key":"ref4","first-page":"126","article-title":"A 4 GSample\/s 8b ADC in <formula formulatype=\"inline\"><tex Notation=\"TeX\">$0.35~\\mu \\hbox{m}$<\/tex><\/formula> CMOS","author":"poulton","year":"2002","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref3","first-page":"544","article-title":"A 24 GS\/s 6b ADC in 90 nm CMOS","author":"schvan","year":"2008","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref6","first-page":"542","article-title":"A 32 mW 1.25 GS\/s 6b 2b\/step SAR ADC in <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$0.13~\\mu \\hbox{m}$<\/tex><\/formula> CMOS","author":"cao","year":"2008","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref5","first-page":"322","article-title":"A 2 GS\/s 6b ADC in <formula formulatype=\"inline\"><tex Notation=\"TeX\">$0.18~\\mu \\hbox{m}$<\/tex><\/formula> CMOS","author":"jiang","year":"2003","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/49.761034"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234315"},{"key":"ref2","first-page":"436","article-title":"A 12.5 Gb\/s SerDes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery","author":"harwood","year":"2007","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref1","first-page":"570","article-title":"A 4 GS\/s 4b flash ADC in <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$0.18~\\mu \\hbox{m}$<\/tex><\/formula> CMOS","author":"park","year":"2006","journal-title":"Int Solid-State Circuits Conf Dig"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.50307"},{"key":"ref20","first-page":"333","article-title":"A 43 mW single-channel 4 GS\/s 4-bit flash ADC in <formula formulatype=\"inline\"><tex Notation=\"TeX\">$0.18~\\mu \\hbox{m}$<\/tex><\/formula> CMOS","author":"sheikhaei","year":"2007","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280860"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6085808\/05941014.pdf?arnumber=5941014","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:54:08Z","timestamp":1642006448000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5941014\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":21,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2011.2157742","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,12]]}}}