{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T22:16:08Z","timestamp":1648851368622},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2011,9,1]],"date-time":"2011-09-01T00:00:00Z","timestamp":1314835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/tcsi.2011.2162459","type":"journal-article","created":{"date-parts":[[2011,9,15]],"date-time":"2011-09-15T05:19:12Z","timestamp":1316063952000},"page":"2010-2016","source":"Crossref","is-referenced-by-count":0,"title":["The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM"],"prefix":"10.1109","volume":"58","author":[{"given":"Jente B.","family":"Kuang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeremy D.","family":"Schaub","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fadi H.","family":"Gebara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dieter","family":"Wendel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Frohnel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudesh","family":"Saroop","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sani","family":"Nassif","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Nowka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433815"},{"key":"ref3","first-page":"252","article-title":"A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65 nm CMOS","author":"chang","year":"0","journal-title":"Dig 2007 Symp VLSI Circuits"},{"key":"ref10","year":"2008","journal-title":"Scannable Dynamic Logic Latch Circuit"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892153"},{"key":"ref11","article-title":"POWER7&#x2122; local clocking and clocked storage elements","author":"warnock","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"356","article-title":"A 0.5 V 100 MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias","author":"nii","year":"0","journal-title":"IEEE ISSCC 2010 Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434074"},{"key":"ref8","first-page":"140","article-title":"High performance 32 nm SOI CMOS with high-k\/metal gate and 0.149 mm<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$^2$<\/tex><\/formula> SRAM and ultra low-k back end with eleven levels of copper","author":"greene","year":"2009","journal-title":"Symp VLSI Technol Dig Tech Papers"},{"key":"ref7","first-page":"17","article-title":"A 32 nm 0.5 V-supply dual-read 6T SRAM","author":"kuang","year":"2010","journal-title":"Proc IEEE Custom Integrated Circuits"},{"key":"ref2","first-page":"344","article-title":"A 32 KB 2R\/1W L1 data cache in 45 nm SOI technology for the POWER7 processor","author":"pille","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034082"},{"key":"ref1","article-title":"A 5.6 GHz 64 KB dual-read data cache for the POWER6 processor","author":"davis","year":"2006","journal-title":"Proc ISSCC"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6016553\/06009214.pdf?arnumber=6009214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:39Z","timestamp":1633909659000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6009214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":12,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2011.2162459","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,9]]}}}