{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,1,6]],"date-time":"2024-01-06T21:59:04Z","timestamp":1704578344799},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2011,9,1]],"date-time":"2011-09-01T00:00:00Z","timestamp":1314835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/tcsi.2011.2163981","type":"journal-article","created":{"date-parts":[[2011,9,16]],"date-time":"2011-09-16T02:42:57Z","timestamp":1316140977000},"page":"2051-2060","source":"Crossref","is-referenced-by-count":19,"title":["Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences"],"prefix":"10.1109","volume":"58","author":[{"given":"Khurram","family":"Waheed","sequence":"first","affiliation":[]},{"given":"Robert Bogdan","family":"Staszewski","sequence":"additional","affiliation":[]},{"given":"Fikret","family":"Dulger","sequence":"additional","affiliation":[]},{"given":"Mahbuba S.","family":"Ullah","sequence":"additional","affiliation":[]},{"given":"Socrates D.","family":"Vamvakos","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681882"},{"key":"ref11","year":"2008","journal-title":"Hybrid Stochastic Gradient Based Digitally Controlled Oscillator Gain Estimation"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014941"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS.2006.321040"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/18.59924"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2002.807092"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117932"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040306"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537261"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617430"},{"key":"ref4","first-page":"344","article-title":"A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction","author":"wu","year":"2008","journal-title":"Proc IEEE Solid-State Circuits Conf (ISSCC'03)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585972"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"220","DOI":"10.1109\/TCSII.2005.858754","article-title":"1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS","volume":"53","author":"staszewski","year":"2006","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref2","first-page":"150","article-title":"A 2 MHz bandwidth low noise RF all digital PLL with 12 ps resolution time-to-digital converter","author":"tonietto","year":"2006","journal-title":"Proc Eur Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS.2009.5505727"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2035411"},{"key":"ref22","author":"smith","year":"1998","journal-title":"HDL Chip Design a Practical Guide for Designing Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog"},{"key":"ref21","first-page":"321","article-title":"A 65 nm CMOS DCXO system for generating 38.4 MHz and a real time clock from a single crystal in 0.9 mm<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$^2$<\/tex><\/formula>","author":"griffith","year":"2010","journal-title":"Proc IEEE Radio Freq Integr Circuits (RFIC) Symp"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2010.5477376"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6016553\/06012495.pdf?arnumber=6012495","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:49:33Z","timestamp":1633909773000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6012495\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":23,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2011.2163981","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,9]]}}}