{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:50:47Z","timestamp":1761663047056},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2012,7,1]],"date-time":"2012-07-01T00:00:00Z","timestamp":1341100800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Circuits Syst. I"],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1109\/tcsi.2011.2177005","type":"journal-article","created":{"date-parts":[[2012,3,2]],"date-time":"2012-03-02T08:57:35Z","timestamp":1330678655000},"page":"1384-1395","source":"Crossref","is-referenced-by-count":34,"title":["Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization"],"prefix":"10.1109","volume":"59","author":[{"given":"Wenbo","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yun","family":"Chiu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672081"},{"key":"ref38","first-page":"289","article-title":"An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters","author":"liu","year":"2007","journal-title":"Proc ASICON"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"140","DOI":"10.1109\/TCSI.2003.821301","article-title":"Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs","volume":"51","author":"leger","year":"2004","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.921882"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/81.915383"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/19.6060"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.821306"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249429"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856291"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2004.834046"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560315"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537536"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560312"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052844"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051512"},{"key":"ref20","first-page":"542","article-title":"A 32 mW 1.25 GS\/s 6b 2b\/step SAR ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"cao","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917427"},{"key":"ref21","first-page":"72","article-title":"A 1.2 V 30 mW 8b 800 MS\/s time-interleaved ADC in 65 nm CMOS","author":"tu","year":"2008","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2019161"},{"key":"ref23","first-page":"82","article-title":"A 600 MS\/s 30 mW 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization","author":"liu","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref26","first-page":"296","article-title":"A 2.6 mW 6b 2.2 GS\/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS","author":"verbruggen","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008477"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/19.668271"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2092170"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.821300"},{"key":"ref11","first-page":"258","article-title":"A 150 MS\/s 8b 71 mW time-interleaved ADC in 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex> <\/formula> CMOS","author":"limotyrakis","year":"2004","journal-title":"Proc ISSCC"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2011.5741157"},{"key":"ref12","first-page":"264","article-title":"A 6b 600 MS\/s 10 mW ADC array in digital 90 nm CMOS","author":"draxelmayr","year":"2004","journal-title":"Proc ISSCC"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"2365","DOI":"10.1109\/TCSI.2004.838154","article-title":"Gain and offset mismatch calibration in time-interleaved multipath A\/D sigma-delta modulators","volume":"51","author":"ferragina","year":"2004","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"532","DOI":"10.1109\/JSSC.2004.841033","article-title":"A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging","volume":"40","author":"jiang","year":"2005","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"1072","DOI":"10.1109\/TMTT.2005.843487","article-title":"Comprehensive digital correction of mismatch errors for a 400-MSamples\/s 80-dB SFDR time-interleaved ADC","volume":"53","author":"seo","year":"2005","journal-title":"IEEE Trans Microw Theory Tech"},{"key":"ref16","first-page":"574","article-title":"A 6b 600 MS\/s 5.3 mW asynchronous ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex> <\/formula> CMOS","author":"chen","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref17","first-page":"576","article-title":"A 1 GS\/s 11b time-interleaved ADC in 0.13 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"gupta","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref18","first-page":"464","article-title":"An 11b 800 MS\/s time-interleaved ADC with digital background calibration","author":"hsu","year":"2007","journal-title":"Proc ISSCC"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.905293"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.735530"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.735531"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.933460"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.364430"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804327"},{"key":"ref7","first-page":"166","article-title":"4 GSample\/s 8b ADC in 0.35 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex> <\/formula> CMOS","author":"poulton","year":"2002","journal-title":"Proc ISSCC"},{"key":"ref49","first-page":"62","article-title":"An error-correcting 14b\/20 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu s$<\/tex><\/formula> CMOS A\/D converter","author":"boyacigiller","year":"1981","journal-title":"Proc ISSCC"},{"key":"ref9","first-page":"318","article-title":"A 20 GS\/s 8b ADC with a 1 MB memory in 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"poulton","year":"2003","journal-title":"ISSCC"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1992.854935"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2158706"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/4.261994"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425736"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048140"},{"key":"ref41","first-page":"38","article-title":"A continuous-time, jitter insensitive <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\sum\\Delta$<\/tex><\/formula> modulator using a digitally linearized Gm-C integrator with embedded SC feedback DAC","author":"kim","year":"2011","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2151510"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2163556"}],"container-title":["IEEE Transactions on Circuits and Systems I: Regular Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8919\/6224221\/06161615.pdf?arnumber=6161615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:50:53Z","timestamp":1633909853000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6161615\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7]]},"references-count":51,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tcsi.2011.2177005","relation":{},"ISSN":["1549-8328","1558-0806"],"issn-type":[{"value":"1549-8328","type":"print"},{"value":"1558-0806","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,7]]}}}